Multirange, +5V, 12-Bit DAS with

2-Wire Serial Interface

6

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TIMING CHARACTERISTICS (continued)

Note 1:

Supply Rejection test.

Note 2:

Note 3:

Ground “on” channel, sine wave applied to all “off” channels.

Note 4:

Guaranteed by design. Not tested.

Note 5:

Use static external load during conversion for specified accuracy.

Note 6:

Tested using internal reference.

Note 7:

PSRR measured at full scale. Tested for the ±10V (MAX127) and ±4.096V (MAX128) input ranges.

Note 8:

Not subject to production testing. Provided for design guidance only.

PARAMETERS

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

Low Period of the SCL Clock

4.7

µs

High Period of the SCL Clock

4.0

µs

Setup Time for a Repeated

START Condition

4.7

µs

Data Hold Time

0

0.9

µs

Data Setup Time

250

ns

Rise Time for Both SDA and SCL

Signals (Receiving)

1000

ns

Fall Time for Both SDA and SCL

Signals (Receiving)

300

ns

Fall Time for Both SDA and SCL

Signals (Transmitting)

up to 6mA sink

20 +

250

ns

Setup Time for STOP Condition

4.0

µs

Capacitive Load for Each

Bus Line

400

pF

Pulse Width of Spike Suppressed

0

50

ns

Hold Time (Repeated) START

Condition

4.0

µs

Bus Free Time Between a STOP

and START Condition

4.7

µs

SCL Clock Frequency

100

kHz

2-WIRE STANDARD MODE