265ksps, +3V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

16

______________________________________________________________________________________

acquisition cycle of the next conversion, and then read-

ing the results of the previous conversion from the bus.

This technique (Figure 10) allows a conversion to be

completed every 16 clock cycles. Note that the switch-

ing of the data bus during acquisition or conversion can

cause additional supply noise, which may make it diffi-

cult to achieve true 12-bit performance.

Layout, Grounding, and Bypassing

For best performance, use printed circuit (PC) boards.

Wire-wrap configurations are not recommended since

the layout should ensure proper separation of analog

and digital traces. Do not run analog and digital lines

parallel to each other, and don’t lay out digital signal

paths underneath the ADC package. Use separate

analog and digital PC board ground sections with only

one “star point” (Figure 11) connecting the two ground

systems (analog and digital). For lowest noise opera-

tion, ensure the ground return to the star ground’s

power supply is low impedance and as short as possi-

ble. Route digital signals far away from sensitive analog

and reference inputs.

impair operation of the ADC’s fast comparator. Bypass

capacitors, 0.1µF and 4.7µF, located as close as to the

MAX1295/MAX1297’s power-supply pin as possible.

Minimize capacitor lead length for best supply-noise

rejection and add an attenuation resistor (5

Ω) if the

power supply is extremely noisy.

Figure 11. Power-Supply and Grounding Connections

Figure 10. Timing Diagram for Fastest Conversion

+3V

+3V

GND

SUPPLIES

DGND

+3V

COM

GND

4.7

µF

0.1

µF

DIGITAL

CIRCUITRY

MAX1295

MAX1297

*R = 5

Ω

*OPTIONAL

CLK

ACQUISITION

CONTROL WORD

CONVERSION

D11–D0

ACQUISITION

SAMPLING INSTANT

12

3

4

5

6

7

8

9

10

11

12

13

14

15

16

WR

RD

D7–D0

STATE







CONTROL

WORD

D11–

D0