+2.7V to +5.25V, Low-Power, 10-Bit

Serial ADCs in SO-8

4

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TIMING CHARACTERISTICS

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offset have been calibrated.

Note 3: Offset nulled.

Note 4: Sample tested to 0.1% AQL.

Note 5: External load should not change during conversion for specified accuracy.

Note 6: Guaranteed by design. Not subject to production testing.

time needed for the signal to be acquired.

DOUT

DOUT

6k

DGND

6k

DGND

+2.7V

DOUT

DOUT

6k

DGND

6k

DGND

+2.7V

Figure 1. Load Circuits for DOUT Enable Time

Figure 2. Load Circuits for DOUT Disable Time

MAX124_ _M

MAX124_ _C/E

Figure 1,

CONDITIONS

ns

240

CS Fall to Output Enable

ns

20

200

µs

1.5

Acquisition Time

SCLK Fall to Output Data Valid

ns

240

CS Pulse Width

ns

0

DOUT Rise to SCLK Rise (Note 6)

ns

50

SCLK Low to CS Fall Setup Time

ns

240

CS Rise to Output Disable

MHz

0

2.1

SCLK Clock Frequency

ns

200

SCLK Pulse Width High

ns

200

SCLK Pulse Width Low

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

20

240