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MAX1243BESA Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX1243BESA Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 12 page +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 4 _______________________________________________________________________________________ TIMING CHARACTERISTICS (VDD = +2.7V to +5.25V, circuit of Figure 9, TA = TMIN to TMAX, unless otherwise noted.) Note 1: Tested at VDD = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. Note 3: Offset nulled. Note 4: Sample tested to 0.1% AQL. Note 5: External load should not change during conversion for specified accuracy. Note 6: Guaranteed by design. Not subject to production testing. Note 7: Measured as [VFS (VDD(min)) - VFS (VDD(max))]. Note 8: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. DOUT DOUT 6k DGND CLOAD = 50pF CLOAD = 50pF 6k DGND +2.7V b) High-Z to VOL and VOH to VOL a) High-Z to VOH and VOL to VOH DOUT DOUT 6k DGND CLOAD = 50pF CLOAD = 50pF 6k DGND +2.7V b) VOLto High-Z a) VOH to High-Z Figure 1. Load Circuits for DOUT Enable Time Figure 2. Load Circuits for DOUT Disable Time MAX124_ _M MAX124_ _C/E Figure 1, CLOAD = 50pF Figure 1, CLOAD = 50pF CS = VDD (Note 8) Figure 2, CLOAD = 50pF CONDITIONS ns 240 tDV CS Fall to Output Enable ns 20 200 tDO µs 1.5 tACQ Acquisition Time SCLK Fall to Output Data Valid ns 240 tCS CS Pulse Width ns 0 tSTR DOUT Rise to SCLK Rise (Note 6) ns 50 tCS0 SCLK Low to CS Fall Setup Time ns 240 tTR CS Rise to Output Disable MHz 0 2.1 fSCLK SCLK Clock Frequency ns 200 tCH SCLK Pulse Width High ns 200 tCL SCLK Pulse Width Low UNITS MIN TYP MAX SYMBOL PARAMETER 20 240 |
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