signal. At the end of the acquisition interval, the T/H

switches move to the hold position retaining the charge

During the conversion interval, the switched capacitive

DAC adjusts to restore the comparator input voltage to

0V within the limits of a 12-bit resolution. This action

requires 12 conversion clock cycles and is equivalent

digital representation of the analog input signal.

Sufficiently low source impedance is required to ensure

an accurate sample. A source impedance of up to 1.5k

Ω

does not significantly degrade sampling accuracy. To

minimize sampling errors with higher source impedances,

connect a 100pF capacitor from the analog input to GND.

This input capacitor forms an RC filter with the source

impedance limiting the analog-input bandwidth. For larg-

er source impedances, use a buffer amplifier to maintain

analog-input signal integrity and bandwidth.

When operating in internal clock mode, the T/H circuitry

enters its tracking mode on the eighth rising clock edge

of the address byte, see the Slave Address section. The

T/H circuitry enters hold mode on the falling clock edge of

the acknowledge bit of the address byte (the ninth clock

pulse). A conversion, or series of conversions, are then

internally clocked and the MAX1236–MAX1239 holds

SCL low. With external clock mode, the T/H circuitry

enters track mode after a valid address on the rising

edge of the clock during the read (R/W = 1) bit. Hold

mode is then entered on the rising edge of the second

clock pulse during the shifting out of the first byte of the

result. The conversion is performed during the next 12

clock cycles.

The time required for the T/H circuitry to acquire an

input signal is a function of the input sample capaci-

tance. If the analog-input source impedance is high,

the acquisition time constant lengthens and more time

must be allowed between conversions. The acquisition

to be acquired. It is calculated by:

Analog Input Bandwidth

The MAX1236–MAX1239 feature input-tracking circuitry

with a 5MHz small-signal bandwidth. The 5MHz input

bandwidth makes it possible to digitize high-speed tran-

sient events and measure periodic signals with band-

widths exceeding the ADC’s sampling rate by using

under sampling techniques. To avoid high-frequency

signals being aliased into the frequency band of interest,

anti-alias filtering is recommended.

Analog Input Range and Protection

Internal protection diodes clamp the analog input to

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/12-Channel, 2-Wire Serial, 12-Bit ADCs

10

______________________________________________________________________________________

TRACK

AIN0

AIN1

AIN2

AIN3/REF

GND

ANALOG INPUT MUX

CAPACITIVE

DAC

REF

CAPACITIVE

DAC

REF

MAX1236

MAX1237

HOLD

TRACK

HOLD

Figure 4. Equivalent Input Circuit