5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

6

_______________________________________________________________________________________

ns

240

ns

ns

20

240

SCLK Fall to Output Data Valid

CONDITIONS

240

CS Fall to Output Enable

ns

240

CS Rise to Output Disable

CS Fall to SSTRB Output Enable

(Note 6)

ns

240

CS Rise to SSTRB Output

Disable (Note 6)

Internal clock mode only

ns

0

SSTRB Rise to SCLK Rise

(Note 6)

ns

0

DIN to SCLK Hold

µs

1.5

Acquisition Time

ns

100

DIN to SCLK Setup

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

TIMING CHARACTERISTICS

ns

100

CS to SCLK Rise Setup

ns

0

CS to SCLK Rise Hold

ns

200

SCLK Pulse Width High

ns

200

SCLK Pulse Width Low

ns

240

SCLK Fall to SSTRB

Note 1:

Note 2:

Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is

calibrated.

Note 3:

Internal reference, offset nulled.

Note 4:

On-channel grounded; sine-wave applied to all off-channels.

Note 5:

Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6:

Guaranteed by design. Not subject to production testing.

Note 7:

Note 8:

External load should not change during the conversion for specified accuracy.

Note 9:

Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND (Figure 12c);

REFADJ = GND.

Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (

CS high). When the outputs are

active (

Note 12: Measured at VL = 2.7V and VL = 3.6V.