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MAX1204BEPP Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX1204BEPP Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 24 page CLOAD = 100pF 5V, 8-Channel, Serial, 10-Bit ADC with 3V Digital Interface 6 _______________________________________________________________________________________ External clock mode only, CLOAD = 100pF ns 240 CLOAD = 100pF ns ns 20 240 tDO SCLK Fall to Output Data Valid CONDITIONS 240 tDV CS Fall to Output Enable CLOAD = 100pF ns 240 tTR CS Rise to Output Disable tSDV CS Fall to SSTRB Output Enable (Note 6) External clock mode only, CLOAD = 100pF ns 240 tSTR CS Rise to SSTRB Output Disable (Note 6) Internal clock mode only ns 0 tSCK SSTRB Rise to SCLK Rise (Note 6) ns 0 tDH DIN to SCLK Hold µs 1.5 tACQ Acquisition Time ns 100 tDS DIN to SCLK Setup UNITS MIN TYP MAX SYMBOL PARAMETER TIMING CHARACTERISTICS (VDD = +5V ±5%, VL = 2.7V to 3.6V, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) ns 100 tCSS CS to SCLK Rise Setup ns 0 tCSH CS to SCLK Rise Hold ns 200 tCH SCLK Pulse Width High ns 200 tCL SCLK Pulse Width Low CLOAD = 100pF ns 240 tSSTRB SCLK Fall to SSTRB CLOAD = 100pF Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar input mode. Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated. Note 3: Internal reference, offset nulled. Note 4: On-channel grounded; sine-wave applied to all off-channels. Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: Guaranteed by design. Not subject to production testing. Note 7: Common-mode range for analog inputs is from VSS to VDD. Note 8: External load should not change during the conversion for specified accuracy. Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND (Figure 12c); REFADJ = GND. Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled ( CS high). When the outputs are active ( CS low), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB. Note 11: Measured at VSUPPLY +5% and VSUPPLY -5% only. Note 12: Measured at VL = 2.7V and VL = 3.6V. |
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