M13S5121632A-2S datasheet(7/48 Pages) ESMT

Part #	M13S5121632A-2S

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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7 / 48 page

ESMT

M13S5121632A (2S)

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2014

Revision : 1.1

7/48

IDD Specifications

Version

Symbol

-5

-6

Unit

IDD0

90

80

mA

IDD1

110

100

mA

IDD2P

8

mA

IDD2F

50

mA

IDD2Q

50

mA

IDD3P

45

40

mA

IDD3N

80

70

mA

IDD4R

130

120

mA

IDD4W

130

120

mA

IDD5

140

130

mA

IDD6

6

mA

IDD7

220

210

mA

Input / Output Capacitance

Parameter

Package

Symbol

Min

Max

Delta Cap

(max)

Unit

Note

Input capacitance (A0~A12, BA0~BA1,

CKE, CS , RAS , CAS , WE )

TSOP

CIN1

3

5.5

0.5

pF

1,4

Input capacitance (CLK, CLK )

TSOP

CIN2

4

5

0.25

pF

1,4

Data & DQS input/output capacitance

TSOP

COUT

2

5.5

0.5

pF

1,2,3,4

Input capacitance (DM)

TSOP

CIN3

3

5

0.5

pF

1,2,3,4

Notes:

1. These values are guaranteed by design and are tested on a sample basis only.

2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and

DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.

3. Unused pins are tied to ground.

4. This parameter is sampled. VDDQ = 2.5V ± 0.2V, VDD = 2.5V ± 0.2V. f=100MHz, TA =25°C, VOUT(DC) = VDDQ/2, VOUT

(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to

facilitate trace matching at the board level).

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M13S5121632A-2S Datasheet(PDF) 7 Page - Elite Semiconductor Memory Technology Inc.

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