M13S64164A-2Y datasheet(7/49 Pages) ESMT

Part #	M13S64164A-2Y

Description	Double-data-rate architecture, two data transfers per clock cycle

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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7 / 49 page

ESMT

M13S64164A (2Y)

Automotive Grade

Elite Semiconductor Memory Technology Inc.

Publication Date : Oct. 2012

Revision : 1.0

7/49

IDD Specifications

Version

Symbol

-4

-5

-6

Unit

IDD0

75

65

55

mA

IDD1

85

75

65

mA

IDD2P

8

mA

IDD2F

40

35

30

mA

IDD2Q

40

35

30

mA

IDD3P

15

mA

IDD3N

70

60

50

mA

IDD4R

130

120

110

mA

IDD4W

120

110

100

mA

IDD5

70

60

50

mA

IDD6

3

mA

IDD7

150

130

110

mA

Input / Output Capacitance

Parameter

Package

Symbol

Min

Max

Delta Cap

(max)

Unit

Note

TSOP

2

4

pF

Input capacitance (A0~A11, BA0~BA1,

CKE, CS , RAS , CAS , WE )

BGA

CIN1

TBD

0.5

pF

1,4

TSOP

2

4

pF

Input capacitance (CLK, CLK )

BGA

CIN2

TBD

0.25

pF

1,4

TSOP

2

6

pF

Data & DQS input/output capacitance

BGA

COUT

TBD

0.5

pF

1,2,3,4

TSOP

2

4

pF

Input capacitance (DM)

BGA

CIN3

TBD

0.5

pF

1,2,3,4

Notes:

1. These values are guaranteed by design and are tested on a sample basis only.

2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and

DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.

3. Unused pins are tied to ground.

4. This parameter is sampled. For all devices, VDDQ = 2.5V ± 0.2V, VDD = 2.5V ± 0.2V. f=100MHz, TA =25°C, VOUT(DC) =

VDDQ/2, VOUT (peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in

loading (to facilitate trace matching at the board level).

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M13S64164A-2Y Datasheet(PDF) 7 Page - Elite Semiconductor Memory Technology Inc.

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