12-Bit, 30Msps, TTL-Output ADC

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9

AGND and DGND are the two grounds available on the

MAX1172. These two internal grounds are isolated on

the device. The use of ground planes is recommended

to achieve optimum device performance. DGND is

the return path for all digital output logic interfaces.

AGND and DGND should be separated from each

other and connected together only at the device

through a ferrite bead.

A Schottky or hot carrier diode connected between

due to potential power-supply sequencing latchup con-

ditions. Use of the recommended interface circuit shown

in Figure 2 will provide optimum device performance for

the MAX1172.

Voltage Reference

The MAX1172 requires the use of two voltage refer-

typical) is the force for the bottom of the voltage refer-

ence ladder. Both voltages are applied across an inter-

nal reference ladder resistance of 800

Ω. The +2.5V

ed to 20mA maximum if a different driving circuit is

used in place of the recommended reference circuit

shown in Figures 2 and 3.

be driven to the expected ideal values, as is commonly

done with standard flash converters. A decoupling

capacitor of 0.01µF connected to AGND from each tap

is recommended to minimize high-frequency noise

injection.

The analog input range will scale proportionally with

respect to the reference voltage if a different input

range is required. The maximum scaling factor for

device operation is ±20% of the recommended refer-

MAX1172 is laser trimmed to optimize performance

with ±2.5V references, its accuracy will degrade if

operated beyond a ±2% range.

An example of a recommended reference driver circuit

is shown in Figure 2. IC1 is REF-03, the +2.5V refer-

ence with a tolerance of 0.6% or ±0.015V. The 10k

Ω

potentiometer supports an adjustable range of 150mV.

IC2 is recommended to be an OP-07 or equivalent

device. R2 and R3 must be matched to within 0.1%

with good TC tracking to maintain a 0.3LSB matching

The following errors are defined:

+FS error = top of ladder offset voltage

=

-FS error = bottom of ladder offset voltage

=

Where the +FS (full scale) input voltage is defined as

the output 1LSB above the transition of 1–10 and 1–11,

and the -FS input voltage is defined as the output 1LSB

below the transition of 0–00 and 0–01.

Figure 3. Analog Equivalent Input Circuit