10-Bit, 20Msps, TTL-Output ADC

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7

COARSE

ADC

SUCCESSIVE

INTERPOLATION

STAGE 1

SUCCESSIVE

INTERPOLATION

STAGE N

ANALOG

PRESCALER

DIGITAL

OUTPUTS

FB

+5V

-5.2V

+5V

R1

10k

R2

30k

R3

30k

R4

10k

1

µF

0.01

µF

0.01

µF

1

µF

10

µF

10

µF

1

µF

C1

0.01

µF

C2

0.01

µF

C3

0.01

µF

C4

0.01

µF

C6

0.1

µF

C7

0.1

µF

C8

0.1

µF

C9

0.1

µF

C10

0.01

µF

C11

0.01

µF

C5

0.01

µF

VIN

(±2V)

±2.5V MAX

CLK

(TTL)

VIN

VFT

VIN

CLK

VST

VRM

VSB

VFB

GND

VOUT

VTRIM

R5

100

Ω

2.5V

1

3

2

4

6

7

8

R

2R

2R

2R

2R

R

D1

-5.2V

= AGND

+5V

= DGND

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

2

4

5

6

NOTES:

1) D1 = SCHOTTKY OR HOT CARRIER DIODE

2) FB = FERRITE BEAD, FAIR RITE #2743001111

TO BE MOUNTED AS CLOSELY TO THE DEVICE

AS POSSIBLE. THE FERRITE BEAD TO ADC

CONNECTION SHOULD NOT BE SHARED WITH

ANY OTHER DEVICE.

3) C1–C11 = CHIP CAPACITOR (RECOMMENDED)

MOUNTED AS CLOSE TO DEVICE'S PIN AS

POSSIBLE.

IS NOT RECOMMENDED.

5) R5 PROVIDES CURRENT LIMITING TO 45mA.

(OVERRANGE)

(MSB)

(LSB)

4

-2.5V

MAX1160

IC1

IC2

OP07

MAX6225

Figure 2. Typical Operating Circuit

The following errors are defined:

+FS error = top of ladder offset voltage

=

∆(+FS - VST + 1LSB)

-FS error = bottom of ladder offset voltage

=

∆(-FS - VSB - 1LSB)

where the +FS (full-scale) input voltage is defined as the

output transition between 11 1111 1110 and 11 1111 1111,

and the -FS input voltage is defined as the output transi-

tion between 00 0000 0000 and 00 0000 0001 (Table 2).

Analog Input

VIN is the analog input. The full-scale input range will

be 80% of the reference voltage, or ±2V with VFB =

-2.5V and VFT = +2.5V.

The analog input’s drive requirements are minimal

when compared to conventional flash converters. This

is due to the MAX1160’s extremely low (5pF) input

capacitance and very high (300k

Ω) input resistance.

For example, for an input signal of ±2Vp-p with a

10MHz input frequency, the peak output current

required for the driving circuit is only 628µA.

Clock Input

The MAX1160 is driven from a single-ended TTL input

between 20ns and 300ns to ensure proper operation of

the internal track/hold amplifier (Figure 1a). When oper-

ating the MAX1160 at sampling rates above 3Msps, it is

recommended that the clock input duty cycle be kept at