400ksps, +5V, 8-/4-Channel, 10-Bit ADCs

with +2.5V Reference and Parallel Interface

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11

Table 1. Control Byte Functional Description

NAME

FUNCTION

D4

0

SGL/DIF

SGL/DIF = 0: Pseudo-Differential Analog Input Mode

SGL/DIF = 1: Single-Ended Analog Input Mode

In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage

difference between two channels is measured (Tables 2 and 3).

1

0

D3

UNI/BIP

Standby Power-Down Mode. Clock mode is unaffected.

0

1

1

UNI/BIP = 0: Bipolar Mode

UNI/BIP = 1: Unipolar Mode

D2, D1, D0

Normal Operation Mode. External clock mode is selected.

1

A2, A1, A0

Address bits A2–A0 select which of the 8/4 (MAX1090/MAX1092) channels is to be converted

(Tables 3 and 4).

Normal Operation Mode. Internal clock mode is selected.

BIT

PD1, PD0

0

D7, D6

PD1 and PD0 select the various clock and power-down modes.

Full Power-Down Mode. Clock mode is unaffected.

D5

ACQMOD

ACQMOD = 0: Internal Acquisition Mode

ACQMOD = 1: External Acquisition Mode

sition interval or initiate a combined acquisition plus

conversion. The sampling interval occurs at the end of

the acquisition interval. The ACQMOD (acquisition

mode) bit in the input control byte (Table 1) offers two

options for acquiring the signal: an internal and an

external acquisition. The conversion period lasts for 13

clock cycles in either the internal or external clock or

acquisition mode. Writing a new control byte during a

conversion cycle will abort the conversion and start a

new acquisition interval.

Internal Acquisition

Select internal acquisition by writing the control byte

with the ACQMOD bit cleared (ACQMOD = 0). This

causes the write pulse to initiate an acquisition interval

whose duration is internally timed. Conversion starts

when this acquisition interval (three external clock

cycles or approximately 1µs in internal clock mode)

ends (Figure 4). When the internal acquisition is com-

bined with the internal clock, the aperture jitter can be

as high as 200ps. Internal clock users wishing to

achieve the 50ps jitter specification should always use

external acquisition mode.

External Acquisition

Use external acquisition mode for precise control of the

sampling aperture and/or dependent control of acquisi-

tion and conversion times. The user controls acquisition

and start-of-conversion with two separate write pulses.

The first pulse, written with ACQMOD = 1, starts an

acquisition interval of indeterminate length. The second

write pulse, written with ACQMOD = 0 (all other bits in

the control byte are unchanged), terminates acquisition

and starts conversion on WR rising edge (Figure 5).

The address bits for the input multiplexer must have the

same values on the first and second write pulses.

Power-down mode bits (PD0, PD1) can assume new

values on the second write pulse (see the Power-Down

Modes section). Changing other bits in the control byte

will corrupt the conversion.

Reading a Conversion

A standard interrupt signal, INT, is provided to allow the

MAX1090/MAX1092 to flag the µP when the conversion

has ended and a valid result is available. INT goes low

when the conversion is complete and the output data

is ready (Figures 4 and 5). INT returns high on the first

read cycle or if a new control byte is written.

Selecting Clock Mode

The MAX1090/MAX1092 operate with an internal or

external clock. Control bits D6 and D7 select either

internal or external clock mode. The part retains the

last-requested clock mode if a power-down mode is

selected in the current input word. For both internal and

external clock modes, internal or external acquisition