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MAX1082AEUE Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX1082AEUE Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 24 page 300ksps/400ksps, Single-Supply, 4-Channel, Serial 10-Bit ADCs with Internal Reference 10 ______________________________________________________________________________________ Pin Description Positive Supply Voltage VDD2 16 Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to VDD1. REFADJ 9 Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped- ance when CS is high. SSTRB 12 Serial-Data Input. Data is clocked in at SCLK’s rising edge. DIN 13 Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and SSTRB are high impedance. CS 14 Serial-Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty cycle must be 40% to 60%.) SCLK 15 Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the reference buffer provides a 2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD1. REF 8 Ground GND 10 Serial-Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high. DOUT 11 Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA (typ). SHDN 7 Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be stable to ±0.5LSB. COM 6 PIN Positive Supply Voltage VDD1 1 FUNCTION NAME VDD2 3k GND DOUT CLOAD 20pF CLOAD 20pF GND 3k DOUT a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL VDD2 3k GND DOUT CLOAD 20pF CLOAD 20pF GND 3k DOUT a) VOH to High-Z b) VOL to High-Z Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time Sampling Analog Inputs CH0–CH3 2–5 |
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