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MAX108 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part No. MAX108
Description  ±5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________
5
AC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 1.5Gsps, fIN at -1dBFS, TA = +25°C,
unless otherwise noted.)
DIV4 mode
DIV1, DIV2 modes
7.5
DIV4 mode
DIV1, DIV2 modes
Figures 6, 7, 8
tPDP
Auxiliary Port Pipeline
Delay
tPDA
9.5
Clock
Cycles
Figures 6, 7, 8
8.5
DREADY to DATA Propagation
Delay (Note 14)
tPD2
-50
150
350
ps
Figure 17
CLK to DREADY Propagation
Delay
tPD1
2.2
ns
Figure 17
Reset Input Data Hold Time
(Note 13)
tHD
0
ps
Figure 15
Clock Pulse Width High
tPWH
0.3
5
ns
Figure 17
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Aperture Jitter
tAJ
<0.5
ps
Aperture Delay
tAD
100
ps
Reset Input Data Setup Time
(Note 13)
tSU
0
ps
DATA Rise Time
tRDATA
420
ps
Maximum Sample Rate
fMAX
1.5
Gsps
Clock Pulse Width Low
tPWL
0.3
ns
DATA Fall Time
tFDATA
360
ps
DREADY Rise Time
tRDREADY
220
ps
DREADY Fall Time
tFDREADY
180
ps
Primary Port Pipeline
Delay
7.5
Clock
Cycles
CONDITIONS
Figure 4
Figure 4
Figure 15
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
Figure 17
TIMING CHARACTERISTICS
Note 1:
Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256 times the slope of the line.
Note 2:
The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3:
The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings
on the CLK+ and CLK- inputs.
Note 4:
Input logic levels are measured with respect to the VCCO power-supply voltage.
Note 5:
All PECL digital outputs are loaded with 50
Ω to VCCO - 2.0V. Measurements are made with respect to the VCCO power-
supply voltage.
Note 6:
The current in the VCCO power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the VTT termination voltage.
Note 7:
Common-mode rejection ratio (CMRR) is defined as the ratio of the change in the transfer-curve offset voltage to the
change in the common-mode voltage, expressed in dB.
Note 8:
Power-supply rejection ratio (PSRR) is defined as the ratio of the change in the transfer-curve offset voltage to the change
in power-supply voltage, expressed in dB.
Note 9:
Measured with the positive supplies tied to the same potential; VCCA = VCCD = VCCI. VCC varies from +4.75V to +5.25V.
Note 10: VEE varies from -5.25V to -4.75V.




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