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MAX106 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part No. MAX106
Description  ±5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
_______________________________________________________________________________________
5
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
Figure 17
Figure 17
Figure 15
Figure 15
Figure 4
Figure 17
ps
220
tRDREADY
DREADY Rise Time
ps
360
tFDATA
DATA Fall Time
ps
420
tRDATA
DATA Rise Time
ps
-50
150
350
tPD2
DREADY to DATA Propagation
Delay (Note 14)
ns
2.2
tPD1
CLK to DREADY Propagation
Delay
ps
0
tHD
Reset Input Data Hold Time
(Note 13)
ps
0
tSU
Reset Input Data Setup Time
(Note 13)
ps
< 0.5
tAJ
Aperture Jitter
ps
100
tAD
Aperture Delay
DIV1, DIV2 modes
DIV1, DIV2 modes
20% to 80%, CL = 3pF
9.5
Clock
Cycles
8.5
tPDA
Auxiliary Port Pipeline Delay
Clock
Cycles
7.5
tPDP
Primary Port Pipeline Delay
ps
180
tFDREADY
DREADY Fall Time
AC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 600Msps, fIN at -1dBFS, TA = +25°C,
unless otherwise noted.)
Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256
· slope of the line.
Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings on
the CLK+ and CLK- inputs.
Note 4: Input logic levels are measured with respect to the VCCO power-supply voltage.
Note 5: All PECL digital outputs are loaded with 50
Ω to VCCO - 2.0V. Measurements are made with respect to the VCCO power-
supply voltage.
Note 6: The current in the VCCO power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the VTT termination voltage.
Note 7: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the
common-mode voltage, expressed in dB.
Note 8: Measured with the positive supplies tied to the same potential, VCCA = VCCD = VCCI. VCC varies from +4.75V to +5.25V.
Note 9: VEE varies from -5.25V to -4.75V.
Note 10: Power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power
supply voltage, expressed in dB.
Note 11: Effective number of bits (ENOB) and signal-to-noise plus distortion (SINAD) are computed from a curve fit referenced to the
theoretical full-scale range.
7.5
Msps
600
fMAX
Maximum Sample Rate
Figure 17
ns
0.75
tPLW
Clock Pulse Width Low
Figure 17
ns
0.75
5
tPWH
Clock Pulse Width High
TIMING CHARACTERISTICS
Figures 6, 7, 8
Figures 6, 7, 8
DIV4 mode
DIV4 mode




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