2.7V to 5.5V, Low-Power, 4-/12-Channel

2-Wire Serial 8-Bit ADCs

_______________________________________________________________________________________

5

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Setup Time for a Repeated START

Condition (Sr)

160

ns

Data Hold Time

(Note 12)

0

150

ns

Data Setup Time

10

ns

Rise Time of SCL Signal

(Current Source Enabled)

(Note 13)

20

80

ns

Rise Time of SCL Signal After

Acknowledge Bit

(Note 13)

20

160

ns

Fall Time of SCL Signal

(Note 13)

20

80

ns

Rise Time of SDA Signal

(Note 13)

20

160

ns

Fall Time of SDA Signal

(Note 13)

20

160

ns

Setup Time for STOP Condition

160

ns

Capacitive Load for Each Bus Line

400

pF

Pulse Width of Spike Suppressed

010

ns

ured for unipolar, single-ended inputs.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offsets have been calibrated.

Note 3: Offset nulled.

Note 4: Ground ON channel; sine wave applied to all OFF channels.

Note 5: Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not

include acquisition time. SCL is the conversion clock in the external clock mode.

Note 7: When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor.

Note 8: The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675

Ω.

Operating Characteristics.

Note 11: Power-supply rejection ratio is measured as:

Power-supply rejection ratio is measured as:

SCL’s falling edge (Figure 1).

VV

VV

V

VV

FS

FS

N

REF

55

45

2

55

45

..

..

−

VV

V

V

V

VV

FS

FS

N

REF

33

27

2

33

27

..

..

−