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MAX104 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part No. MAX104
Description  ±5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________
5
Note 1:
Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256
· slope of the line.
Note 2:
The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3:
The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings
on the CLK+ and CLK- inputs.
Note 4:
Input logic levels are measured with respect to the VCCO power-supply voltage.
Note 5:
All PECL digital outputs are loaded with 50
Ω to VCCO - 2.0V. Measurements are made with respect to the VCCO power-
supply voltage.
Note 6:
The current in the VCCO power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the VTT termination voltage.
Note 7:
Common-Mode Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in
the common-mode voltage, expressed in dB.
Note 8:
Power-Supply Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in
power-supply voltage, expressed in dB.
Note 9:
Measured with the positive supplies tied to the same potential; VCCA = VCCD = VCCI. VCC varies from +4.75V to +5.25V.
Note 10: VEE varies from -5.25V to -4.75V.
AC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 1Gsps, fIN at -1dBFS, TA = +25°C,
unless otherwise noted.)
Figure 17
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
20% to 80%, CL = 3pF
Figure 15
Figure 4
Figure 4
CONDITIONS
Clock
Cycles
7.5
Primary Port Pipeline
Delay
ps
180
tFDREADY
DREADY Fall Time
ps
220
tRDREADY
DREADY Rise Time
ps
360
tFDATA
DATA Fall Time
ns
0.45
tPWL
Clock Pulse Width Low
Gsps
1
fMAX
Maximum Sample Rate
ps
420
tRDATA
DATA Rise Time
ps
0
tSU
Reset Input Data Setup Time
(Note 13)
ps
100
tAD
Aperture Delay
ps
<0.5
tAJ
Aperture Jitter
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Figure 17
ns
0.45
5
tPWH
Clock Pulse Width High
Figure 15
ps
0
tHD
Reset Input Data Hold Time
(Note 13)
Figure 17
ns
2.2
tPD1
CLK to DREADY Propagation
Delay
Figure 17
ps
-50
150
350
tPD2
DREADY to DATA Propagation
Delay (Note 14)
8.5
Figures 6, 7, 8
Clock
Cycles
9.5
tPDA
Auxiliary Port Pipeline
Delay
tPDP
Figures 6, 7, 8
TIMING CHARACTERISTICS
DIV1, DIV2 modes
DIV4 mode
7.5
DIV1, DIV2 modes
DIV4 mode




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