Monolithic CMOS Analog Multiplexers

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7

DG508A

DG509A

EN

+5V

SWITCH

OUTPUT

35pF

1k

Ω

ALL S

AND DA

DB, D

+2.4V

+15V

A0, A1, (A2)

GND

-15V

50

Ω

LOGIC

INPUT

V-

Figure 3. Break-Before-Make Test Circuit

(EN)

(EN)

3V

LOGIC INPUT

SWITCH

OUTPUT

(SEE FIG. 1)

TRANSITION

TIME

SWITCH

OUTPUT

(SEE FIG. 2)

TIME

SWITCH

OUTPUT

(SEE FIG. 3)

OPEN TIME

(B.B.M INTERVAL)

50%

0

50%

0V

0

0

Figure 4. Timing Diagram for Figures 1, 2, and 3

Table 1a. DG508A Truth Table

A2

A1

A0

EN

ON SWITCH

X

X

X

0

NONE

00

0

1

1

00

1

1

2

01

0

1

3

01

1

1

4

10

0

1

5

10

1

1

6

11

0

1

7

11

1

1

8

Table 1 b. DG509A Truth Table

A1

A0

EN

ON SWITCH

X

X

0

NONE

0011

0112

1013

1114

X = Don’t care.

X = Don’t care.