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DS1859 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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DS1859 Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 10 page Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors _____________________________________________________________________ 5 Note 10: After this period, the first clock pulse is generated. Note 11: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 13: CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Note 14: Guaranteed by design. Typical Operating Characteristics (VCC = 5.0V, TA = +25°C, for both 50k Ω and 20kΩ versions, unless otherwise noted.) TEMPERATURE ( °C) 40 60 80 20 0 -20 560 600 640 680 720 520 -40 100 SUPPLY CURRENT vs. TEMPERATURE SDA = SCL = VCC SUPPLY CURRENT vs. VOLTAGE VOLTAGE (V) 5.0 4.5 4.0 3.5 450 500 550 600 650 700 400 3.0 5.5 SDA = SCL = VCC RESISTANCE vs. SETTING SETTING (DEC) 200 150 100 50 10 20 30 40 50 60 0 0250 50k Ω VERSION RESISTANCE vs. SETTING SETTING (DEC) 200 150 100 50 5 10 15 20 0 0250 20k Ω VERSION ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY SCL FREQUENCY (kHz) 300 200 100 600 640 680 720 760 560 0400 SDA = VCC RESISTOR 0 INL (LSB) SETTING (DEC) 225 200 150 175 50 75 100 125 25 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0250 |
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