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LP6217 Datasheet(PDF) 5 Page - Lowpower Semiconductor inc |
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LP6217 Datasheet(HTML) 5 Page - Lowpower Semiconductor inc |
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5 / 6 page  Preliminary LP6217 LP6217 –00 Version 1.0 Datasheet Sep.-2010 www.lowpowersemi.com Page 5 of 6 Operation Information Output Voltage The error amplifier compares a sample of the dc-dc converter output voltage with the 0.6V (VREF) reference and generates an error signal for the PWM comparator. Output voltage of dc-dc converter is setting with the resistor divider by the following equation: Vout=(R1/R2+1) X 0.6V Oscillator The switching frequency of LP6217 up to operate at either 1MHz. Soft Start The soft start is functional after power on. The interval of soft start time is determined by a capacitor connected to SS pin. When EN pin is taken high, the soft start capacitor (CSS) is charged by a constant current of 4μA (typ). During this interval, the SS voltage directly controls the peak inductor current. The maximum load current is available after the soft-start interval is completed. Once the EN pin is taken low, the soft-start capacitor is discharged to ground to prepare for next start-up. The load must wait for the soft-start interval to finish before drawing a significant amount of load current. The duration after which the load can begin to draw maximum load current is: EN The LP6217 can be turn off to reduce the supply current to 0.1μA when EN is low. In this mode, the internal reference, error amplifier, comparators, and biasing circuitry turn off while the N-channel MOSFET is turned off. The boost converter’s output is connected to VCC by the external inductor and catch diode. Output Current Capability The output current capability of the LP6217 is a function of current limit, input voltage, operation frequency, and inductor value. Because of the slope compensation used to stabilize the feedback loop, the duty cycle affects the current limit. The output current capability is governed by the following equation: Current Limitation The internal power-MOS switch current is monitored cycle-by-cycle and is limited to the value not exceed 2A (Typ.). When the switch current reaches the limited value, the internal power-MOS is turned off immediately until the next cycle. A resistor between OCP and GND pin programs peak switch current. The resistor value should be between 10k and 100k. The current limit will be set from 2.5A to 0.5A. Keep traces at this pin as short as possible. Do not put capacitance at this pin. Layout considerations Typical for all switching power supplies, the layout is an important step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully done, the regulator might show noise problem sand duty cycle jitter. The input capacitor should be placed as close as possible to the input pin for good input voltage viltering. The inductor and diode should be placed as close as possible to the switch pin to minimize the noise coupling into other circuits. Since the feedback pin and network is a high impedance circuit the feedback network should be routed away from the inductor. The feedback pin and feedback network should be shielded with a ground plane or trace to minimize noise coupling into this circuit. |
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