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P4C1681-35LMB Datasheet(PDF) 5 Page - Pyramid Semiconductor Corporation |
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P4C1681-35LMB Datasheet(HTML) 5 Page - Pyramid Semiconductor Corporation |
5 / 10 page P4C1681, P4C1682 Page 5 of 10 Document # SRAM109 REV A -12 -15 -20 -25 -35 Min Max Min Max Min Max Min Max Min Max t WC Write Cycle Time 12 15 18 20 30 ns t CW Chip Enable Time 12 15 18 20 25 ns to End of Write t AW Address Valid to 12 15 18 20 25 ns End of Write t AS Address Set-up 0 0 0 0 0 ns Time t WP Write Pulse Width 12 15 18 20 25 ns t AH Address Hold 0 0 0 0 0 ns Time t DW Data Valid to 7 8 10 10 15 ns End of Write t DH Data Hold Time 0 0 0 0 0 ns t WZ Write Enable to 4 5 7 7 13 ns Output in High Z† t OW Output Active to 0 0 0 0 0 ns End of Write t AWE Write Enable to 12 15 20 25 30 ns Data-out Valid£ t ADV Data-in Valid to 12 15 20 25 30 ns Data-out Valid † P4C1682 only. £ P4C1681 only. AC ELECTRICAL CHARACTERISTICS—WRITE CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) 12. Write Cycle Time is measured from the last valid address to the first transitioning address. 10. CE and WE must be LOW for WRITE cycle. 11. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. Symbol Parameter Unit WRITE CYCLE NO. 1 (WE WE WE WE WE controlled)(10) Notes: |
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