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P4C1299-35LMB Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation |
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P4C1299-35LMB Datasheet(HTML) 6 Page - Pyramid Semiconductor Corporation |
6 / 11 page P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM Page 6 Document # SRAM144 REV OR AC TEST COnDITIOnS TRUTH TABLE TIMIng WAVEFORM OF WRITE CYCLE nO. 2 (CE COnTROLLED)(10) Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 Mode CE 1 CE 2 WE OE I/O Power Deselect/Power-Down H x x x High Z Standby x H x x Read L L H L Data Out Active Write L L L x Data In Active Deselect L L H H High Z Active |
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