P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM

Page 5

Document #SRAM144 REV OR

AC CHARACTERISTICS—WRITE CYCLE

(V

(2)

Sym Parameter

-15

-20

-25

-35

-45

Unit

Min Max Min Max Min Max Min Max Min Max

t

WC

Write Cycle Time

10

12

15

20

25

ns

t

CW

Chip Enable Time to End of Write

8

10

12

15

18

ns

t

AW

Address Valid to End of Write

8

10

12

15

18

ns

t

AS

Address Setup Time

0

0

0

0

0

ns

t

WP

Write Pulse Width

8

10

12

15

18

ns

t

AH

Address Hold Time

0

0

0

0

0

ns

t

DW

Data Valid to End of Write

7

8

10

12

15

ns

t

DH

Data Hold Time

0

0

0

0

0

ns

t

WZ

Write Enable to Output in High Z

6

7

8

10

15

ns

t

OW

Output Active from End of Write

0

0

0

0

0

ns

Notes:

10. CE

11. OE is LOW for this WRITE cycle to show t

12. If CE

in a high impedance state

13. Write Cycle Time is measured from the last valid address to the first

transitioning address.