Electronic Components Datasheet Search |
|
PYA28C256E-12LMB Datasheet(PDF) 2 Page - Pyramid Semiconductor Corporation |
|
PYA28C256E-12LMB Datasheet(HTML) 2 Page - Pyramid Semiconductor Corporation |
2 / 14 page PYA28C256 - 32K x 8 EEPROM Page 2 Document # EEPROM104 REV 03 OPERATIOn READ Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE re- turning HIGH. This two line control architecture elimi- nates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. BYTE WRITE Write operations are initiated when both CE and WE are LOW and OE is HIGH. The PYA28C256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically con- tinue to completion. PAgE WRITE The page write feature of the PYA28C256 allows 1 to 64 bytes of data to be consecutively written to the PY- A28C256 during a single internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A 6 through A14) for each subsequent valid write cycle to the part during this opera- tion must be the same as the initial page address. The bytes within the page to be written are specified with the A 0 through A5 inputs. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional 1 to 63 bytes in the same man- ner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 150µs of the falling edge of the pre- ceding WE. If a subsequent WE HIGH to LOW transition is not detected within 150µs, the internal automatic pro- gramming cycle will commence. There is no page write window limitation. Effectively, the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 150µs. WRITE STATUS BITS The PYA28C256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown below. DATA POLLIng The PYA28C256 features DATA Polling as a method to in- dicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the PYA28C256, eliminating additional interrupts or external hardware. Dur- ing the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O 7 (i.e., write data=0xxx xxxx, read data=1xxx xxxx). Once the programming cycle is complete, I/O 7 will reflect true data. Note: If the PYA28C256 is in the pro- tected state and an illegal write operation is attempted, DATA Polling will not operate. TOggLE BIT The PYA28C256 also provides another method for deter- mining when the internal write cycle is complete. During the internal programming cycle, I/O 6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for addtional read or write operations. DATA PROTECTIOn Pyramid has incorporated both hardware and software features that will protect the memory against inadvertent writes during transitions of the host system power sup- ply. Hardware Protection Hardware features protect against inadvertent writes to the PYA28C256 in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay - once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. Software Data Protection A software controlled data protection feature has been implemented on the PYA28C256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the PYA28C256 is shipped from Pyramid with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to the three specific addresses (refer to "Software Data Protection" algorithm). After writing the 3-byte com- mand sequence and after tWC the entire PYA28C256 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the PYA28C256. This is done by preceding the data to be written by the same |
Similar Part No. - PYA28C256E-12LMB |
|
Similar Description - PYA28C256E-12LMB |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |