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PYA28C64 Datasheet(PDF) 2 Page - Pyramid Semiconductor Corporation |
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PYA28C64 Datasheet(HTML) 2 Page - Pyramid Semiconductor Corporation |
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2 / 10 page  PYA28C64 - 8K x 8 EEPROM Page 2 Document # EEPROM105 REV B Grade(2) Ambient Temp GND V CC Military -55°C to +125°C 0V 5.0V ± 10% OPERATION READ Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE re- turning HIGH. This two line control architecture elimi- nates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. BYTE WRITE Write operations are initiated when both CE and WE are LOW and OE is HIGH. The PYA28C64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically con- tinue to completion. CHIP CLEAR The contents of the entire memory of the PYA28C64 may be set to the high state by the CHIP CLEAR operation. By setting CE low and OE to 12 volts, the chip is cleared when a 10 msec low pulse is applied to WE. DEVICE IDENTIFICATION An extra 32 bytes of EEPROM memory are available to the user for device identification. By raising A 9 to 12 ± 0.5V and using address locations 1FE0H to 1FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. DATA POLLING The PYA28C64 features DATA Polling as a method to in- dicate to the host system that the byte write cycle has completed. DATA Polling allows a simple bit test opera- tion to determine the status of the PYA28C64, eliminat- ing additional interrupts or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O 7 (i.e., write data=0xxx xxxx, read data=1xxx xxxx). Once the programming cycle is complete, I/O 7 will reflect true data. READY/BUSY Pin 1 is an open drain RDY/BUSY output that can be used to detect the end of a write cycle. RDY/BUSY is actively pulled low during the write cycle and is released at the completion of the write. The open drain connec- tion allows for OR-tying of several devices to the same RDY/BUSY line. The RDY/BUSY pin is not connected for the PYA28C64X. Sym Parameter Value Unit V CC Power Supply Pin with Respect to GND -0.3 to +6.25 V V TERM Terminal Voltage with Respect to GND (up to 6.25V) -0.5 to +6.25 V T A Operating Temperature -55 to +125 °C T BIAS Temperature Under Bias -55 to +125 °C T STG Storage Temperature -65 to +150 °C P T Power Dissipation 1.0 W I OUT DC Output Current 50 mA MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDITIONS CAPACITANCES(4) (V CC = 5.0V, TA = 25°C, f = 1.0MHz) Sym Parameter Conditions Typ Unit C IN Input Capacitance V IN = 0V 10 pF C OUT Output Capacitance V OUT = 0V 10 pF |
Similar Part No. - PYA28C64 |
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Similar Description - PYA28C64 |
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