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M30805SGP Datasheet(PDF) 35 Page - Mitsubishi Electric Semiconductor |
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M30805SGP Datasheet(HTML) 35 Page - Mitsubishi Electric Semiconductor |
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35 / 315 page  Under development Preliminary Specifications REV.B Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M16C/80 (144-pin version) group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control 35 Item Status Oscillation ON _____ _____ _____ _______ RD/WR signal, address bus, data bus, CS, BHE Floating Programmable I/O ports P0, P1, P2, P3, P4, P5 Maintains status when hold signal is received P6, P7, P8, P9, P10 __________ HLDA Output “L” Internal peripheral circuits ON (but watchdog timer stops) ALE signal Undefined (7) External bus status when accessing to internal area Table 1.7.9 shows external bus status when accessing to internal area Table 1.7.9. External bus status when accessing to internal area (6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to __________ the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status __________ __________ is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.7.8 shows the microcomputer status in the hold state. The bus is used in the following descending order of __________ priority: HOLD, DMAC, CPU. _____ ________ Figure 1.7.4. Example of RD signal extended by RDY signal __________ HOLD > DMAC > CPU Table 1.7.8. Microcomputer status in hold state Item SFR accessing status Internal ROM/RAM accessing status Address bus Remain address of external area accessed immediately before Data bus When read Floating When write Floating _____ ______ ________ _________ RD, WR, WRL, WRH Output "H" ________ BHE Remain external area status accessed immediately before ____ CS Output "H" ALE ALE output (8) BCLK output BCLK output can be selected by bit 7 of the processor mode register 0 (address 000416 :PM07) and bit 1 and bit 0 of the system clock select register 0 (address 000616 :CM01, CM00). Setting PM07 to “0” and CM01 and CM00 to “002” outputs the BCLK signal from P53. However, in single chip mode, BCLK signal is not output. When setting PM07 to “1”, the function is as set by CM01 and CM00. |
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