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DS130402

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

SZA-5044(Z)

Pin

Function

Description

1, 3,

5, 9,

11,

15, 17

N/C

Pins are not used. May be grounded, left open, or connected to adjacent pin.

6VPC1

VPC1 is the bias control pin for the stage 1 active bias circuit and can be run from 2.9Vto5V control. An external series

resistor is required for proper setting of bias levels depending on control voltage. Refer to the evaluation board sche-

matic for resistor value. To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage

applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10mA.

7VPC2

VPC2 is the bias control pin for the stage 2 active bias circuit and can be run from 2.9Vto5V control. An external series

resistor is required for proper setting of bias levels depending on control voltage. Refer to the evaluation board sche-

matic for resistor value. To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage

applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10 mA.

8VPC3

VPC3 is the bias control pin for the stage 3 active bias circuit and can be run from 2.9Vto5V control. An external series

resistor is required for proper setting of bias levels depending on control voltage. Refer to the evaluation board sche-

matic for resistor value. To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage

applied to pin 20 (Vbias) unless Vpc supply current capability is less than 10mA.

10

VDET

Output power detector voltage. Load with 10Kto100K

Ω to ground for best performance.

2, 4

RF IN

RF input pins. This is DC grounded internal to the IC. Do not apply voltage to this pin. All three pins must be used for

proper operation.

12,

13,14

RF OUT

RF output pin. This is also another connection to the 3rd stage collector

16

VC3

3rd stage collector bias pin. Apply 5V to this pin.

18

VC2

2nd stage collector bias pin. Apply 5V to this pin.

19

VC1

1st stage collector bias pin. Apply 5V to this pin.

20

VBIAS

Active bias network VCC. Apply 5V to this pin.

EPAD

GND

Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for optimum

thermal and RF performance. Several vias should be located under the EPAD as shown in the recommended land pat-

tern (page 5).