CS5124

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8

APPLICATION INFORMATION

UVLO and Thermal Shutdown Interaction

The UVLO pin and thermal shutdown circuit share the

same internal comparator. During high temperature

thermal shutdown circuit. This interaction increases the

turn−on threshold (and hysteresis) of the UVLO circuit. If

the UVLO pin shuts down the IC during high temperature

operation, higher hysteresis (see hysteresis specification)

might be required to enable the IC.

BIAS Pin

main application diagram in Figure 1. In order to provide

adequate phase margin for the bias control loop, the pole

capacitor should be kept above 10 kHz. The frequency of

this pole can be calculated by Formula (1).

Pole Frequency +

Transconductance of pass Transistor

2

p

CV(CC)

(1)

The Line BIAS pin shows a significant change in the

show up as poor line regulation with a low value pull−up

shown in Figure 3.

5.0 mΑ

10 mΑ

20 mΑ

50 mΑ

100 mΑ

200 mΑ

7.9

8.0

8.1

8.2

8.3

The BIAS pin and associated components form a high

impedance node. Care should be taken during PCB layout to

avoid connections that could couple noise into this node. To

differential between the two values is specified (see

electrical characteristcs).

Gate Drive

Rail to rail gate driver operation can be obtained (up to

13.5 V) over a range of MOSFET input capacitance if the

gate resistor value is kept low. Figure 5 shows the high gate

driving an IRF220.

Figure 4. Gate Drive vs. Gate Resistor Driving an

0

Gate Resistor Value

8.5

0.3

0.5

2.5

5.0

8.0

7.5

7.0

6.5

6.0

11

A large negative dv/dt on the power MOSFET drain will

couple current into the gate driver through the gate to drain

capacitance. If this current is kept within absolute maximum

ratings for the GATE pin it will not damage the IC. However

if a high negative dv/dt coincides with the start of a PWM

duty cycle, there will be small variations in oscillator

frequency due to current in the controller substrate. If

required, this can be avoided by choosing the transformer

ratio and reset circuit so that a high dv/dt does not coincide

with the start of a PWM cycle, or by clamping the negative

voltage on the GATE pin with a Schottky diode

First Current Sense Threshold

During normal operation the peak primary current is

control loop) and the current sense network. Once the signal

the PWM cycle terminates. During high output currents the

current sense threshold determines the maximum signal

terminated. Under this condition the maximum peak current

ramp, the PWM comparator offset voltage and the PWM on

time. The nominal first current threshold varies with on time

and can be calculated from Formulas (2) and (3) below.

1st Threshold +

2.9 V * 170 mV ms

TON

10

* 60 mV

(2)

to exceed the first threshold, the PWM cycle terminates

early and the converter begins to function more like a current

source. The current sense network must be chosen so that the

peak current during normal operation does not exceed the

first current sense threshold.

Second Current Sense Threshold

The second threshold is intended to protect the converter

from overheating by switching to a low duty cycle mode

when there are abnormally high fast rise currents in the