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M30800FCGP Datasheet(PDF) 9 Page - Mitsubishi Electric Semiconductor |
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M30800FCGP Datasheet(HTML) 9 Page - Mitsubishi Electric Semiconductor |
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9 / 317 page  Under development Preliminary Specifications REV.D Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M16C/80 (100-pin version) group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description 9 Pin Description Signal name Function Pin name I/O type I/O port P5 Input/output Input/output Input/output Input/output Input/output Input/output Input Input/output Input/output I/O port P6 I/O port P7 I/O port P8 I/O port P85 I/O port P9 I/O port P10 P50 to P57 P60 to P67 P70 to P77 P80 to P84, P86, P87, P85 P90 to P97 P100 to P107 This is an 8-bit I/O port equivalent to P0. P53 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. Output Output Output Output Output Input Output Input This is an 8-bit I/O port equivalent to P0. When set for input in single chip mode, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistance. In memory expansion and microprocessor mode, an built-in pull-up resistance cannot be used. Pins in this port also function as UART0 and UART1 I/ O pins as selected by software. This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N-channel open drain output). Pins in this port also function as timer A0–A3, timer B5 or UART2 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as UART3 and UART4 I/O pins, Timer B0–B4 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins. Furthermore, P104–P107 also function as input pins for the key input interrupt function. WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”. WR, BHE, and RD selected Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a “L” level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the microcomputer is in the ready state. P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from “H” to “L”. The NMI function cannot be canceled using software. The pull-up cannot be set for this pin. DW, CASL, CASH, RAS Output Output Output Output When accessing to DRAM area while DW signal is “L”, write to DRAM. CASL and CASH show timing when latching to line address. When CASL accesses to even address, and CASH to odd, these two pins become “L”. RAS signal shows timing when latching to row address. P40 to P47 I/O port P4 This is an 8-bit I/O port equivalent to P0. Input/output Output Output CS0 to CS3 These pins output CS0–CS3 signals. CS0–CS3 are chip select signals used to specify an access space. A16 to A22, A23 Output These pins output 8 high-order address bits (A16–A22, A23). Highest address bit (A23) outputs inversely. MA8 to MA12 If accessing to DRAM area, these pins output data separated in time by multiplexing. |
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