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RT6296F Datasheet(PDF) 11 Page - Richtek Technology Corporation |
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RT6296F Datasheet(HTML) 11 Page - Richtek Technology Corporation |
11 / 12 page RT6296F Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS6296F-00 January 2015 www.richtek.com 11 Figure 3. Derating Curve of Maximum Power Dissipation Layout Considerations For best performance of the RT6296F, the following layout guidelines must be strictly followed. Input capacitor must be placed as close to the IC as possible. SW should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. Keep every trace connected to pin as wide as possible for improving thermal dissipation. SW VOUT R1 R2 CIN CIN COUT COUT SW should be connected to inductor by Wide and short trace. Keep sensitive components away from this trace. Suggestion layout trace wider for thermal. Via can help to reduce power trace and improve thermal dissipation. The feedback components must be connected as close to the device as possible. VOUT GND PG SW FB EN/SYNC BOOT VIN PVCC GND Css Input capacitor must be placed as close to the IC as possible. Suggestion layout trace wider for thermal. PVCC Figure 3. PCB Layout Guide 0.0 0.3 0.6 0.9 1.2 1.5 0 25 50 75 100 125 Ambient Temperature (°C) Four-Layer PCB |
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