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PROGRAMMABLE DIGITAL DELAY TIMER August 2001 FEATURES: • Eight timing ranges • Four modes • RC controlled on-chip oscillator • Power-On-Reset (POR) • Reset input for delay abort • Complementary outputs • Delay-in-Progress Indicator output • LS7213 (DIP), LS7213-S (SOIC) - See Figure 1 APPLICATIONS Time delay relays for HVAC equipment and industrial controls. DESCRIPTION The LS7213 is a monolithic CMOS integrated circuit for generating programmable time-delays. The delay is initiated by a logic transi- tion at the Trigger input and the completion of the delay is marked by a change of status at the Out1 and the Out2 outputs. Three in- puts, D1, D2 and D3 select 1-of-8 scale factors, s. The delay, td is related to s by the expression, td = s/frc, where frc is the frequency at the RC input produced by an internal oscillator. An external re- sistor-capacitor pair connected to the RC pin controls the oscillator frequency. There are four modes of operation selected by inputs A and B. The operating modes are: On-Delay (OND), Off-Delay (OFD), Dual-Delay (DLD) and One- Shot(OST). These modes are described below: On-Delay (OND) Mode A positive transition at the Trigger input starts the on-delay timer. At the end of the delay Out1 switches low and Out2 switches high. A negative transition at the Trigger input immediately aborts any on- delay in progress. If the Trigger input is switched low, Out1 if low will switch high and Out2 if high will switch low without delay. The states of Out2 in the preceding description applies only if Flashen input is low at the time of the Trigger input transition. See the Out2 pin section for a complete description. Off-Delay (OFD) Mode A negative transition at the Trigger input starts the off-delay timer. At the end of the delay Out1 switches high and Out2 switches low. A positive transition at the Trigger input immediately aborts any off- delay in progress. If the Trigger input is switched high, Out1 if high will switch low and Out2 if low will switch high without delay. The states of Out2 in the preceding description applies only if Flashen input is low at the time of the Trigger input transition. See the Out2 pin section for a complete description. Dual-Delay (DLD) Mode In Dual-Delay mode, the delay is generated for both positive and negative transitions at the Trigger input. A positive transition at the Trigger input starts the on-delay timer and aborts any off-delay tim- ing in progress. At the end of the delay Out1 switches low and Out2 switches high. A negative transition at the Trigger input starts the off-delay timer and aborts any on-delay timing in progress. At the end of the delay Out1 switches high and Out2 switches low. The states of Out2 in the preceding description applies only if Flashen input is low at the time of the Trigger input transition. See the Out2 pin section for a complete description. One-Shot(OST) Mode A positive transition at the Trigger input causes Out1 to switch low and Out2 to switch high immediately and start the one-shot delay timer. At the end of the delay Out1 switches high and Out2 switches low. Thus in effect, a positive transition at the Trigger in- put produces a negative pulse at Out1 and a positive pulse at Out2. The one-shot delay timer is restarted with every positive trigger transition, thus rendering the Out1 and Out2 pulse-widths stretchable to any duration by periodic re-trigger. A negative tran- sition at the Trigger input has no effect. The states of Out2 in the preceding description applies only if Flashen input is low at the time of the Trigger input transition. See the Out2 pin section for a complete description. INPUTS/OUTPUTS Following is a description of all the input/output pins and their functions. Delay Select Inputs: D1, D2, D3 (Pin3, Pin2, Pin1) The logic states applied to these three inputs enable the user to select a scale factor, s, for generating a delay, td, fromTrigger in- put to Out1/Out2 outputs according to Table1. The delay is given by the expression: td = s/frc, where, s is the scale factor, and frc is the oscillator frequency at the RC input. The sample delays in Table1 are based on an os- cillator frequency, frc=10kHz. TABLE 1. Delay Selection D3 D2 D1 s td (=s/frc) 0 0 0 1x103 0.1sec 0 0 1 1x104 1.0sec 0 1 0 1x105 10.0sec 0 1 1 60x103 0.1min 1 0 0 60x104 1.0min 1 0 1 60x105 10.0min 1 1 0 3600x103 0.1hr 1 1 1 3600x104 1.0hr D1, D2 and D3 inputs have internal pull-down resistors 7213-082101-1 LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 LS7213 1 2 3 4 5 6 7 14 13 12 11 10 9 8 D3 D2 D1 A B FLASHEN VDD (+V) VSS (-V) OUT1 OUT2 RESET RC CAP TRIGGER FIGURE 1 PIN ASSIGNMENT TOP VIEW UL ® A3800 |
