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LS7063 Datasheet(PDF) 4 Page - LSI Computer Systems |
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LS7063 Datasheet(HTML) 4 Page - LSI Computer Systems |
4 / 7 page DYNAMIC ELECTRICAL CHARACTERISTICS: (Refer to Figure 3, Timing Diagram) (VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to +70˚C unless otherwise noted.) PARAMETER SYMBOL MIN MAX UNIT CONDITIONS Count Frequency fc DC 15 MHz - (All Count inputs) Count Pulse Width tCPW 30 - ns Measured at 50% point, (All Count Inputs) Max tr, tf = 10ns Count Rise & Fall time tr, tf - 30 µs - (Pins 2, 16) Count Ripple Time tCR - 4 µs Transition from32 ones to 32 zeros (Pins 2 - LS7061) from negative edge of count pulse Count Ripple Time tCR - 2 µs Transition of 16 bits from (Pin 13 - LS7061) all ones to all zeros from negative edge (Pins 2,13 - LS7063) of count pulse RESET Pulse Width tRPW 500 - ns Measured at 50% point (All Counter Stages Max tr, tf = 200ns Fully Reset) RESET Removal Time tRR - 250 ns Measured from RESET signal at VIH (Reset Removed From All Counter Stages) SCAN Frequency fSC - 1 MHz SCAN Pulse Wildth tSCPW 500 - ns Measured at 50% point Max tr, tf = 100ns SCAN RESET/LOAD tRSCPW 1 - µs Measured at 50% point Pulse Width Max tr, tf = 200ns (All latches loaded and Scan Counter Reset to Least Significant Byte) SCAN RESET/LOAD tRSCR - 250 ns Measured from SCAN RESET/ Removal Time LOAD at VIH (Reset Removed from Scan Counter; Load Command Removed From Latches) Output Disable tDOD - 200 ns Transition to Output High Delay Time Impedance State Measured (B0 - B7) From Scan at VIL or ENABLE at VIH Output ENABLE tDOE - 200 ns Transition to Valid On State Delay Time Measured from Scan at VIH (B0 - B7) and ENABLE at VIL; Delay to Valid Data Levels for COL =10pF and one TTL Load or Valid Data Currents for High Capacitance Loads Output Delay Time tDCE - 300 ns Negative Transition from Scan at VIL CASCADE ENABLE and ST5 of Scan Counter or Positive Transition From SCAN RESET/LOAD at VIL to Valid Data Levels for COL = 10pF and one TTL Load 7061/63-083198-4 |
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