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UPD78C17 Datasheet(PDF) 91 Page - NEC |
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UPD78C17 Datasheet(HTML) 91 Page - NEC |
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91 / 110 page  91 µPD78C17,78C18 AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ±10 %, VSS = AVSS = 0 V) Read/write Operation: PARAMETER SYMBOL TEST CONDITIONS MIN. MAX. UNIT X1 input cycle time tCYC 66 250 ns Address setup time (to ALE ↓ )tAL fXX = 15 MHz, CL = 100 pF 30 ns Address hold time (from ALE ↓ )tLA 35 ns RD ↓ delay time from address tAR 100 ns Address float time from RD ↓ tAFR CL = 100 pF 20 ns Data input time from address tAD fXX = 15 MHz, CL = 100 pF 250 ns Data input time from ALE ↓ tLDR 135 ns Data input time from RD ↓ tRD 120 ns RD ↓ delay time from ALE ↓ tLR 15 ns Data hold time (from RD ↑ )tRDH CL = 100 pF 0 ns ALE ↑ delay time from RD ↑ tRL fXX = 15 MHz, CL = 100 pF 80 ns RD low-level width tRR In Data Read 215 ns fXX = 15 MHz, CL = 100 pF In OP Code Fetch 415 ns fXX = 15 MHz, CL = 100 pF ALE high-level width tLL fXX = 15 MHz, CL = 100 pF 90 ns M1 setup time (to ALE ↓ )tML fXX = 15 MHz 30 ns M1 hold time (from ALE ↓ )tLM 35 ns IO/M setup time (to ALE ↓ )tIL 30 ns IO/M hold time (from ALE ↓ )tLI 35 ns WR ↓ delay time from address tAW fXX = 15 MHz, CL = 100 pF 100 ns Data output time from ALE ↓ tLDW 180 ns Data output time from WR ↓ tWD CL = 100 pF 100 ns WR ↓ delay time from ALE ↓ tLW fXX = 15 MHz, CL = 100 pF 15 ns Data setup time (to WR ↑ )tDW 165 ns Data hold time (from WR ↑ )tWDH 60 ns ALE ↑ delay time from WR ↑ tWL 80 ns WR low-level width tWW 215 ns |
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