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LTC2312-12 Datasheet(PDF) 9 Page - Linear Technology |
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LTC2312-12 Datasheet(HTML) 9 Page - Linear Technology |
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9 / 22 page  LTC2312-12 9 231212fa For more information www.linear.com/LTC2312-12 TiMing DiagraMs block DiagraM 231212 BD 4 – + S/H 2.5V LDO 2 ×/4× 1.024V BANDGAP TIMING LOGIC 1 6 7 8 THREE-STATE SERIAL OUTPUT PORT 12-BIT SAR ADC 2 3 AIN REF VDD OVDD 2.2µF GND ANALOG INPUT RANGE 0V TO VREF ANALOG SUPPLY 3V OR 5V I/O INTERFACE SUPPLY RANGE 1.8V TO 5V 5 2.2µF 2.2µF SDO SCK CONV TS8 PACKAGE ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE 231212 TD04 231312 TD03 231312 TD02 231312 TD01 Hi-Z MSB CONV OVDD/2 SDO t3 Hi-Z CONV OVDD/2 SDO t8 VOH VOL SCK OVDD/2 SDO t7 VOH VOL SCK OVDD/2 SDO t4 Figure 1. SDO Enabled After CONV ↓ Figure 3. SDO Data Valid Hold After SCK ↓ Figure 2. SDO Into Hi-Z After CONV ↑ Figure 4. SDO Data Valid Access After SCK ↓ VOH VOL |
Similar Part No. - LTC2312-12_15 |
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Similar Description - LTC2312-12_15 |
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