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LTC2153-14 Datasheet(PDF) 5 Page - Linear Technology |
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LTC2153-14 Datasheet(HTML) 5 Page - Linear Technology |
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5 / 26 page  5 215314fa LTC2153-14 For more information www.linear.com/LTC2153-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL DATA OUTPUTS VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 247 125 350 175 454 250 mV mV VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l 1.125 1.125 1.250 1.250 1.375 1.375 V V RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω DigiTal inpuTs anD ouTpuTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) MIN TYP MAX UNITS fS Sampling Frequency (Note 9) l 10 310 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 1.5 1.2 1.61 1.61 50 50 ns ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 1.5 1.2 1.61 1.61 50 50 ns ns DIGITAL DATA OUTPUTS MIN TYP MAX UNITS tD ENC to Data Delay CL = 5pF (Note 8) l 1.7 2 2.3 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1.3 1.6 2 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0.3 0.4 0.55 ns Pipeline Latency 6 6 Cycles SPI Port Timing (Note 8) tSCK SCK Period Write Mode Readback Mode CSDO= 20pF, RPULLUP = 2k l l 40 250 ns ns tS CS to SCK Set-Up Time l 5 ns tH SCK to CS Hold Time l 5 ns tDS SDI Set-Up Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 310MHz, differential ENC+/ENC– = 2VP-P sine wave, input range = 1.32VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: Recommended operating conditions. |
Similar Part No. - LTC2153-14_15 |
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Similar Description - LTC2153-14_15 |
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