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L29C525JC20 Datasheet(PDF) 1 Page - LOGIC Devices Incorporated

Part # L29C525JC20
Description  Dual Pipeline Register
Download  6 Pages
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Manufacturer  LODEV [LOGIC Devices Incorporated]
Direct Link  http://www.logicdevices.com
Logo LODEV - LOGIC Devices Incorporated

L29C525JC20 Datasheet(HTML) 1 Page - LOGIC Devices Incorporated

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DEVICES INCORPORATED
L29C525
Dual Pipeline Register
Pipeline Registers
03/23/2000–LDS.29C525-G
1
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u Dual 8-Deep Pipeline Register
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u Configurable to Single 16-Deep
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u Low Power CMOS Technology
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u Replaces AMD Am29525
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u Load, Shift, and Hold Instructions
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u Separate Data In and Data Out Pins
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u Three-State Outputs
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u Package Styles Available:
• 28-pin Plastic DIP
• 28-pin Plastic LCC, J-Lead
FEATURES
DESCRIPTION
L29C525
Dual Pipeline Register
DEVICES INCORPORATED
The L29C525 is a high-speed, low
power CMOS pipeline register. It is
pin-for-pin compatible with the AMD
Am29525. The L29C525 can be
configured as two independent 8-level
pipelines or as a single 16-level
pipeline. The configuration imple-
mented is determined by the instruc-
tion code (I1-0) as shown in Table 2.
The I1-0 instruction code controls the
internal routing of data and loading of
each register. For instruction I1-0 = 00
(Push A and B), data applied at the
D7-0 inputs is latched into register A0
on the rising edge of CLK. The
contents of A0 simultaneously move
to register A1, A1 moves to A2, and so
on. The contents of register A7 are
wrapped back to register B0. The
registers on the B side are similarly
shifted, with the contents of register
B7 lost.
Instruction I1-0 = 01 (Push B) acts
similarly to the Push A and B
instruction, except that only the B side
registers are shifted. The input data is
applied to register B0, and the
contents of register B7 are lost. The
contents of the A side registers are
unaffected. Instruction I1-0 = 10 (Push
A) is identical to the Push B
instruction, except that the A side
registers are shifted and the B side
registers are unaffected.
Instruction I1-0 = 11 (Hold) causes no
internal data movement. It is equiva-
lent to preventing the application of a
clock edge to any internal register.
The contents of any of the registers is
selectable at the output through the
use of the S3-0 control inputs. The
independence of the I and S control
lines allows simultaneous reading and
writing. Encoding for the S3-0 controls
is given in Table 3.
L29C525 BLOCK DIAGRAM
8
OE
Y7-0
D7-0
I1-0
CLK
4
2
S3-0
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
8


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