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LTC694IN8 Datasheet(PDF) 8 Page - Linear Technology |
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LTC694IN8 Datasheet(HTML) 8 Page - Linear Technology |
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8 / 16 page  8 LTC690/LTC691 LTC694/LTC695 S APPLICATI I FOR ATIO the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold. Battery Switchover The battery switchover circuit compares VCC to the VBATT input, and connects VOUT to whichever is higher. When VCC rises to 70mV above VBATT, the battery switchover comparator, C2, connects VOUT to VCC through a charge pumped NMOS power switch, M1. When VCC falls to 50mV above VBATT, C2 connects VOUT to VBATT through a PMOS switch, M2. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to VBATT. The response time of C2 is approximately 20 µs. During normal operation, the LTC690 family uses a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to VOUT from VCC and has a typical on resistance of 5 Ω. The VOUT pin should be bypassed with a capacitor of 0.1 µF or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. When operating currents larger than 50mA are required from VOUT, or a lower dropout (VCC-VOUT voltage differen- tial) is desired, the LTC691 and LTC695 should be used. These products provide BATT ON output to drive the base Microprocessor Reset The LTC690 family uses a bandgap voltage reference and a precision voltage comparator C1 to monitor the 5V supply input on VCC (see Block Diagram). When VCC falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold accounts for a 5% variation on VCC, so the RESET output becomes active low when VCC falls below 4.75V (4.65V typical). On power-up, the RESET signal is held active low for a minimum of 35ms for the LTC690/LTC691 (140ms for the LTC694/LTC695) after reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. The reset active time is adjustable on the LTC691/ LTC695. On power-down, the RESET signal remains ac- tive low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal. The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at VCC pin do not activate the RESET output. Response time is typically 10 µs.Tohelppreventmistriggeringduetotransientloads, VCC pin should be bypassed with a 0.1µF capacitor with the leads trimmed as short as possible. The LTC691 and LTC695 have two additional outputs: RESET and LOW LINE. RESET is an active high output and is the inverse of RESET. LOW LINE is the output of the precision voltage comparator C1. When VCC falls below VCC t1 t1 = RESET ACTIVE TIME V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS t1 V2 V2 V1 V1 690 F01 RESET LOW LINE Figure 1. Reset Active Time |
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