LTC2410C datasheet(7/44 Pages) LINER

Part #	LTC2410C

Description	24-Bit No Latency ADC with Differential Input and Differential Reference

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Manufacturer	LINER [Linear Technology]

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LTC2410

7

TEST CIRCUITS

APPLICATIO S I FOR ATIO

FU CTIO AL BLOCK DIAGRA

Figure 1. LTC2410 State Transition Diagram

CONVERTER OPERATION

Converter Operation Cycle

The LTC2410 is a low power, delta-sigma analog-to-

digital converter with an easy to use 3-wire serial interface.

Its operation is made up of three states. The converter

operating cycle begins with the conversion, followed by

the low power sleep state and ends with the data output

(see Figure 1). The 3-wire interface consists of serial data

output (SDO), serial clock (SCK) and chip select (CS).

Initially, the LTC2410 performs a conversion. Once the

conversion is complete, the device enters the sleep state.

While in this sleep state, power consumption is reduced by

an order of magnitude. The part remains in the sleep state

as long as CS is HIGH. The conversion result is held

indefinitely in a static shift register while the converter is

in the sleep state.

AUTOCALIBRATION

AND CONTROL

DAC

DECIMATING FIR

INTERNAL

OSCILLATOR

SERIAL

INTERFACE

ADC

∑

∫

GND

VCC

IN+

IN–

SDO

SCK

REF+

REF –

CS

FO

(INT/EXT)

2410 FD

–+

+

–

1.69k

SDO

2410 TA04

Hi-Z TO VOL

VOH TO VOL

VOL TO Hi-Z

CLOAD = 20pF

VCC

1.69k

SDO

2410 TA03

Hi-Z TO VOH

VOL TO VOH

VOH TO Hi-Z

CLOAD = 20pF

CONVERT

SLEEP

DATA OUTPUT

2410 F01

TRUE

FALSE

CS = LOW

AND

SCK

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