5

LTC1726

timer is not cleared, a reset pulse will occur. The watch-

dog timer is cleared during a reset and restarts when the

reset is deasserted. When disabling the watchdog func-

ground and WT must be grounded.

RST (Pin 6): Reset Logic Output. Active low, open-drain

one or more of the supplies are below trip thresholds.

After all supplies become valid, the reset remains as-

serted for the period set by the capacitor on the RT pin.

The watchdog timer can also trigger the reset whenever

the watchdog time-out period is exceeded. This pin can

logic.

WT (Pin 7): Watchdog Time-Out Input. Place a capacitor

between this pin and ground to adjust the watchdog time-

out period. To determine the watchdog time-out period:

capacitor will generate a 1s watchdog time-out period.

The watchdog function can be disabled by connecting

this pin to ground.

power to the part when the voltage on this pin is greater

with a 0.1

µF or larger ceramic capacitor.

supplies power to the part when the voltage on this pin is

ground with a 0.1

µF or larger ceramic capacitor.

also supplies power to the part when the voltage on this

ground with a 0.1

µF or larger ceramic capacitor.

GND (Pin 4): Ground.

WDI (Pin 5): Watchdog Input. A logic input whose rising

or falling edge must occur on this pin within the selected

watchdog time-out period or a reset pulse will occur. The

watchdog time-out period is set by the value of the

capacitor that is placed on the WT pin. The rising or falling

edge of this pin clears the voltage on the WT capacitor,

preventing a reset pulse from occurring. If the watchdog

Time-Out Period vs Capacitance

0.1

1

10

10

1726 G12

RST Output Voltage vs

Supply Voltage (LTC1726-2.5)

TYPICAL PERFOR A CE CHARACTERISTICS

0

2

1726 F13

1

1

23

0

3

PI FU CTIO S