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LTC1702CGN Datasheet(PDF) 6 Page - Linear Technology |
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LTC1702CGN Datasheet(HTML) 6 Page - Linear Technology |
6 / 36 page 6 LTC1702 FB2 (Pin 14): Controller 2 Feedback Input. See FB1. COMP2 (Pin 15): Controller 2 Loop Compensation. See COMP1. RUN/SS2 (Pin 16): Controller 2 Run/Soft-start. See RUN/ SS1. FAULT (Pin 17): Output Overvoltage Fault (Latched). The FAULT pin is an open-drain output with an internal 10 µA pull-up. If either regulated output voltage rises more than 15% above its programmed value for more than 25 µs, the FAULT output will go high and the entire LTC1702 will be disabled. When FAULT is high, both BG pins will go high, turning on the bottom MOSFET switches and pulling down the high output voltage. The LTC1702 will remain latched in this state until the power is cycled. When FAULT mode is active, the FAULT pin will be pulled up with an internal 10 µA current source. Tying FAULT directly to PGND will PIN FUNCTIONS disable latched FAULT mode and will allow the LTC1702 to resume normal operation when the overvoltage fault is removed. PGOOD2 (Pin 18): Controller 2 Power Good. See PGOOD1. PGND (Pin 19): Power Ground. The BG n drivers return to this pin. Connect PGND to a high current ground node in close proximity to the sources of external MOSFETs, QB1 and QB2, and the VIN and VOUT bypass capacitors. SW2 (Pin 20): Controller 2 Switching Node. See SW1. TG2 (Pin 21): Controller 2 Top Gate Drive. See TG1. BG2 (Pin 22): Controller 2 Bottom Gate Drive. See BG1. BOOST2 (Pin 23): Controller 2 Top Gate Driver Supply. See BOOST1. IMAX2 (Pin 24): Controller 2 Current Limit Set. See IMAX1. BLOCK DIAGRAM BURST LOGIC SOFT START 90% DUTY CYCLE RUN/SS1,2 COMP1,2 10 µA 3.5 µA 1VP-P 550mV 800mV 760mV 840mV IMAX1,2 DRIVE LOGIC 100 µs DELAY OSC 550kHz + – ILIM FB MIN MAX 920mV FLT DIS FCB FB1,2 1702 BD BOOST1,2 TG1,2 FROM OTHER CONTROLLER SHUTDOWN TO THIS CONTROLLER SHUTDOWN TO ENTIRE CHIP FAULT PVCC 25 µs DELAY FROM OTHER CONTROLLER VCC SW1,2 BG1,2 PGND SGND PGOOD1,2 |
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