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LTC1596AISW Datasheet(PDF) 6 Page - Linear Technology |
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LTC1596AISW Datasheet(HTML) 6 Page - Linear Technology |
6 / 12 page 6 LTC1595/LTC1596/LTC1596-1 TYPICAL PERFOR A CE CHARACTERISTICS PIN FUNCTIONS LTC1595 VREF (Pin 1): Reference Input. RFB (Pin 2): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. OUT1 (Pin 3): Current Output Pin. Tie to inverting input of current to voltage converter op amp. GND (Pin 4): Ground Pin. LD (Pin 5): The Serial Interface Load Control Input. When LD is pulled low, data is loaded from the shift register into the DAC register, updating the DAC output. SRI (Pin 6): The Serial Data Input. Data on the SRI pin is latched into the shift register on the rising edge of the serial clock. Data is loaded MSB first. CLK (Pin 7): The Serial Interface Clock Input. VDD (Pin 8): The Positive Supply Input. 4.5V ≤ VDD ≤ 5.5V. Requires a bypass capacitor to ground. LTC1596/LTC1596-1 OUT1 (Pin 1): True Current Output Pin. Tie to inverting input of current to voltage converter op amp. OUT2 (Pin 2): Complement Current Output Pin. Tie to analog ground. AGND (Pin 3): Analog Ground Pin. STB1, STB2, STB3, STB4 (Pins 4, 8, 10, 11): Serial Interface Clock Inputs. STB1, STB2 and STB4 are rising edge triggered inputs. STB3 is a falling edge triggered input (see Truth Tables). LD1, LD2 (Pins 5, 9): Serial Interface Load Control Inputs. When LD1 and LD2 are pulled low, data is loaded from the shift register into the DAC register, updating the DAC output (see Truth Tables). SRO (Pin 6): The Output of the Shift Register. Becomes valid on the active edge of the serial clock. SRI (Pin 7): The Serial Data Input. Data on the SRI pin is latched into the shift register on the active edge of the serial clock. Data is loaded MSB first. DGND (Pin 12): Digital Ground Pin. CLR (Pin 13): The Clear Pin for the DAC. Clears DAC to zero scale when pulled low on LTC1596. Clears DAC to midscale when pulled low on LTC1596-1. This pin should be tied to VDD for normal operation. VDD (Pin 14): The Positive Supply Input. 4.5V ≤ VDD ≤ 5.5V. Requires a bypass capacitor to ground. VREF (Pin 15): Reference Input. RFB (Pin 16): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. Supply Current vs Logic Input Voltage INPUT VOLTAGE (V) 0 0.6 0.8 1.0 4 1595/96 G10 0.4 0.2 0.5 0.7 0.9 0.3 0.1 0 1 2 3 5 VDD = 5V Logic Threshold vs Supply Voltage SUPPLY VOLTAGE (V) 0 1.0 2.0 3.0 0.5 1.5 2.5 1595/96 G11 10 05 16 27 38 49 |
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