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LTC1657LCGN Datasheet(PDF) 1 Page - Linear Technology |
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LTC1657LCGN Datasheet(HTML) 1 Page - Linear Technology |
1 / 12 page 1 LTC1657L Parallel 16-Bit Rail-to-Rail Micropower DAC April 2000 s 16-Bit Monotonic Over Temperature s 3V Single Supply Operation s Deglitched Rail-to-Rail Voltage Output: 8nV • s s ICC: 650µA Typ s Maximum DNL Error: ±1LSB s Settling Time: 20 µs to ±1LSB s Internal or External Reference s Internal Power-On Reset to 0V s Asynchronous CLR Pin s Output Buffer Configurable for Gain of 1 or 2 s Parallel 16-Bit or 2-Byte Double Buffered Interface s Narrow 28-Lead SSOP Package s 5V Version Available (LTC1657) The LTC ®1657L is a complete single supply, rail-to-rail voltage output, 16-bit digital-to-analog converter (DAC) in a 28-pin SSOP or PDIP package. It includes a rail-to-rail output buffer amplifier, an internal 1.25V reference and a double buffered parallel digital interface. The LTC1657L operates from a 2.7V to 5.5V supply. It has a separate reference input pin that can be driven by an external reference. The full-scale output can be 1 or 2 times the reference voltage depending on how the X1/X2 pin is connected. The LTC1657L is similar to Linear Technology Corporation’s LTC1450 12-bit VOUT DAC family allowing an easy up- grade path. It is the only buffered 16-bit parallel DAC in a 28-lead SSOP package and includes an onboard reference for stand alone performance. FEATURES DESCRIPTION , LTC and LT are registered trademarks of Linear Technology Corporation. s Instrumentation s Industrial Process Control s Automatic Test Equipment s Communication Test Equipment APPLICATIONS Differential Nonlinearity vs Input Code CODE 0 – 1.0 – 0.2 – 0.4 – 0.6 – 0.8 0 0.2 0.4 0.6 0.8 1.0 16484 32768 1657 TA02 49152 65535 Final Electrical Specifications Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. BLOCK DIAGRA REFLO GND 0V TO 2.5V 2.7V TO 5.5V 16-BIT DAC R R 25 REFHI REFOUT 22 24 23 X1/X2 21 20 26 1657 TA01 VOUT VCC D15 (MSB) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 2 28 27 D8 D7 DATA IN FROM MICROPROCESSOR DATA BUS FROM MICROPROCESSOR DECODE LOGIC FROM SYSTEM RESET D0 (LSB) – + REFERENCE 1.25V 16-BIT DAC REGISTER POWER-ON RESET LDAC CLR WR CSMSB CSLSB LSB 8-BIT INPUT REGISTER MSB 8-BIT INPUT REGISTER |
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