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LTC1604AIG Datasheet(PDF) 9 Page - Linear Technology |
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LTC1604AIG Datasheet(HTML) 9 Page - Linear Technology |
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9 / 20 page  9 LTC1604 APPLICATIONS INFORMATION currents are shut down and only leakage current remains (about 1 µA). Wake-up time from Sleep mode is much slower since the reference circuit must power up and settle. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 160ms with the recommended 47 µF capacitor. Shutdown is controlled by Pin 33 (SHDN). The ADC is in shutdown when SHDN is low. The shutdown mode is selected with Pin 32 (CS). When SHDN is low, CS low selects nap and CS high selects sleep. Figure 2a. Nap Mode to Sleep Mode Timing t3 SHDN CS 1604 F02a t4 SHDN CONVST 1604 F02b Figure 2b. SHDN to CONVST Wake-Up Timing t2 t1 CS CONVST RD 1604 F03 Figure 3. CS top CONVST Setup Timing 0 2800 1604 F04 400 800 1600 1200 2000 2400 4 3 2 1 0 CONVST LOW TIME, t5 (ns) tCONV tACQ Figure 4. Change in DNL vs CONVST Low Time. Be Sure the CONVST Pulse Returns High Early in the Conversion or After the End of Conversion Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A falling edge applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. We recommend using a narrow logic low or narrow logic high CONVST pulse to start a conversion as shown in Figures 5 and 6. A narrow low or high CONVST pulse prevents the rising edge of the CONVST pulse from upset- ting the critical bit decisions during the conversion time. Figure 4 shows the change of the differential nonlinearity error versus the low time of the CONVST pulse. As shown, if CONVST returns high early in the conversion (e.g., CONVST low time <500ns), accuracy is unaffected. Simi- larly, if CONVST returns high after the conversion is over (e.g., CONVST low time >tCONV), accuracy is unaffected. For best results, keep t5 less than 500ns or greater than tCONV. Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are in |
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