6

LTC1606

CS (Pin 25): Chip Select. Internally OR’d with R/C. With

R/C low, a falling edge on CS will initiate a conversion.

With R/C high, a falling edge on CS will enable the output

data.

BUSY (Pin 26): Output Shows Converter Status. It is low

when a conversion is in progress. Data valid on the rising

edge of BUSY. CS or R/C must be high when BUSY rises

TEST CIRCUITS

Load Circuit for Access Timing

1k

30pF

30pF

DBN

DBN

1k

5V

1606 TC01

Load Circuit for Output Float Delay

1k

30pF

30pF

DBN

DBN

1k

5V

1606 TC02

16-BIT CAPACITIVE DAC

COMP

REF BUF

1.64x

2.5V REF

CAP

(4.096V)

•

•

•

D15

D0

BUSY

CONTROL LOGIC

R/C

BYTE

INTERNAL

CLOCK

CS

ZEROING SWITCHES

REF

AGND1

AGND2

DGND

16

1606 BD

+

–

SUCCESSIVE APPROXIMATION

REGISTER

OUTPUT LATCHES

4k

7.35k

2.5k

9k

or another conversion will start without time for signal

acquisition.

a 0.1

µF ceramic and a 10µF tantalum capacitor.

27.