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LTC3605A Datasheet(PDF) 6 Page - Linear Technology |
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LTC3605A Datasheet(HTML) 6 Page - Linear Technology |
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6 / 22 page  LTC3605A 6 3605afc For more information www.linear.com/LTC3605A pin FuncTions RT (Pin 1): Oscillator Frequency Programming Pin. Con- nect an external resistor (between 200k to 40k) from RT to SGND to program the frequency from 800kHz to 4MHz. Since the synchronization range is ±30% of set frequency, be sure that the set frequency is within this percentage range of the external clock to ensure frequency lock. PHMODE (Pin 2): Control Input to Phase Selector. Deter- mines the phase relationship between internal oscillator and CLKOUT. Tie it to INTVCC for 2-phase operation, tie it to SGND for 3-phase operation, and tie it to INTVCC/2 for 4-phase operation. MODE (Pin 3): Operation Mode Select. Tie this pin to INTVCC to force continuous synchronous operation at all output loads. Tying it to SGND enables discontinuous mode operation at light loads. Tying this pin to INTVCC/2 shuts off the internal clock during discontinuous intervals. FB (Pin 4): Output Feedback Voltage. Input to the error amplifierthatcomparesthefeedbackvoltagetotheinternal 0.6V reference voltage. This pin is normally connected to a resistive divider from the output voltage. TRACK/SS (Pin 5): Output Tracking and Soft-Start Pin. Allows the user to control the rise time of the output volt- age. Putting a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifier, instead it servos the FB pin to the TRACK voltage. Above 0.6V, the tracking function stops and the internal reference resumes control of the error amplifier. There’s an internal 2.5µA pull-up current from INTVCC on this pin, so putting a capacitor here provides soft-start function. ITH (Pin 6): Error Amplifier Output and Switching Regu- lator Compensation Point. The current comparator’s trip threshold is linearly proportional to this voltage, whose normal range is from 0.3V to 1.8V. Tying this pin to IN- TVCC activates internal compensation and output voltage positioning, raising VOUT to 1.5% higher than the nominal value at IOUT = 0 and 1.5% lower at IOUT = 5A. RUN (Pin 7): Run Control Input. Enables chip operation by tying RUN above 1.2V. Tying it below 1.1V shuts down the part. PGOOD (Pin 8): Output Power Good with Open-Drain Logic. PGOOD is pulled to ground when the voltage on the FB pin is not within ±10% of the internal 0.6V reference. VON (Pin 9): On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output volt- age makes the on-time proportional to VOUT and keeps the switching frequency constant at different VOUT. However, when VON is <0.6V or >6V, then switching frequency will no longer remain constant. PGND (Pin 10, Exposed Pad Pin 25): Power Ground. Return path of internal power MOSFETs. Connect this pin to the negative terminals of the input capacitor and output capacitor. The exposed pad must be soldered to the PCB ground for electrical contact and rated thermal performance. SW (Pins 11 to 16): Switch Node Connection to External Inductor. Voltage swing of SW is from a diode voltage drop below ground to PVIN. PVIN (Pins 17, 18): Power VIN. Input voltage to the on- chip power MOSFETs. SVIN (Pin 19): Signal VIN. Filtered input voltage to the on-chip 3.3V regulator. Connect a (1Ω to 10Ω) resistor between SVIN and PVIN and bypass to GND with a 0.1µF capacitor. BOOST (Pin 20): Boosted Floating Driver Supply for Inter- nal Top Power MOSFET. The (+) terminal of the bootstrap capacitor connects here. This pin swings from a diode voltage drop below INTVCC up to PVIN + INTVCC. INTVCC (Pin 21): Internal 3.3V Regulator Output. The internal power drivers and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 1µF low ESR ceramic capacitor. SGND (Pin 22): Signal Ground Connection. CLKOUT (Pin 23): Output Clock Signal for PolyPhase Operation. The phase of CLKOUT with respect to CLKIN is determined by the state of the PHMODE pin. CLKOUT’s peak-to-peak amplitude is INTVCC to GND. CLKIN (Pin 24): External Synchronization Input to Phase Detector.ThispinisinternallyterminatedtoSGNDwith20k. The phase-locked loop will force the top power NMOS’s turn on signal to be synchronized with the rising edge of the CLKIN signal. |
Similar Part No. - LTC3605A_15 |
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Similar Description - LTC3605A_15 |
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