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LTC1550 Datasheet(PDF) 5 Page - Linear Technology |
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LTC1550 Datasheet(HTML) 5 Page - Linear Technology |
5 / 12 page 5 LTC1550/LTC1551 TYPICAL PERFORMANCE CHARACTERISTICS Spot Noise (See Figure 2, COUT = 10µF) FREQUENCY (kHz) 1 0.01 1 0.1 10 10 100 LTC1550/51 • G12 VCC = 5V IL = 5mA CIN = 4.7µF COUT = 10µF CL = 0.1µF Output Spectrum (See Figure 2, COUT = 22µF) FREQUENCY (Hz) 100k 90 80 70 60 50 40 30 20 10 0 –10 1M 10M LT1550/51 • G13 VCC = 5V IL = 5mA CIN 4.7µF COUT = 22µF CL = 0.1µF Spot Noise (See Figure 2, COUT = 22µF) FREQUENCY (kHz) 1 0.01 1 0.1 10 10 100 LTC1550/51 • G14 VCC = 5V IL = 5mA CIN = 4.7µF COUT = 22µF CL = 0.1µF PIN FUNCTIONS SHDN: Shutdown (TTL Compatible). This pin is active low (SHDN) for the LTC1550 and active high (SHDN) for the LTC1551. When this pin is at VCC (GND for LTC1551), the LTC1550 operates normally. When SHDN is pulled low (high for LTC1551), the LTC1550 enters shutdown mode. In shutdown, the charge pump stops, the output collapses to 0V, and the quiescent current drops typically to 0.2 µA. VCC: Power Supply. VCC requires an input voltage between 4.5V and 6.5V for the fixed voltage LTC1550CS8-4.1/ LTC1551CS8-4.1. The adjustable voltage LTC1550CGN/ LTC1550IGN operates with a VCC range of 2.7V to 6.5V. Output voltage and output load current conditions depend on the VCC supply voltage. Consult the Electrical Charac- teristics table and Typical Performance Characteristics for guaranteed test points. The difference between the input voltage and output should never be set to exceed 14V or damage to the chip may occur. VCC must be bypassed to PGND (GND for 8-pin packages) with at least a 0.1 µF capacitor placed in close proximity to the chip. A 4.7 µF or larger bypass capacitor is recommended to minimize noise and ripple at the output. C1+: C1 Positive Input. Connect a 0.1 µFcapacitorbetween C1+ and C1–. VOUT: Negative Voltage Output. This pin must be bypassed to ground with a 4.7 µF or larger capacitor to ensure regulator loop stability. At least 10 µF is recommended to provide specified output ripple. An additional 0.1 µF low ESR capacitor is recommended to minimize high fre- quency spikes at the output. C1–: C1 Negative Input. Connect a 0.1 µF capacitor from C1+ to C1–. GND: Ground. Connect to a low impedance ground. A ground plane will help minimize regulation errors. CPOUT: Negative Charge Pump Output. This pin requires a 0.1 µF storage capacitor to ground. SENSE: Connect to VOUT. The LTC1550/LTC1551 internal regulator uses this pin to sense the output voltage. For optimum regulation, SENSE should be connected close to the output load. SSOP PACKAGE ONLY PGND: Power Ground. Connect to a low impedance ground. PGND should be connected to the same potential as AGND. AGND: Analog Ground. Connect to a low impedance ground. AGND should be connected to a ground plane to minimize regulation errors. |
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