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LTC1419ISW Datasheet(PDF) 6 Page - Linear Technology |
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LTC1419ISW Datasheet(HTML) 6 Page - Linear Technology |
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6 / 20 page  6 LTC1419 PI FU CTIO S CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): Chip Select. The input must be low for the ADC to recognize CONVST and RD inputs. CS also sets the shutdown mode when SHDN goes low. CS and SHDN low select the quick wake-up nap mode. CS high and SHDN low select sleep mode. BUSY (Pin 25): The BUSY output shows the converter status. It is low when a conversion is in progress. Data valid on the rising edge of BUSY. VSS (Pin 26): –5V Negative Supply. Bypass to AGND with 10 µF tantalum in parallel with 0.1µF or 10µF ceramic. DVDD (Pin 27): 5V Positive Supply. Short to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10 µF tantalum in parallel with 0.1µF or 10µF ceramic. +AIN (Pin 1): ±2.5V Positive Analog Input. –AIN (Pin 2): ±2.5V Negative Analog Input. VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 1 µF. REFCOMP (Pin 4): 4.06V Reference Output. Bypass to AGND with 10 µF tantalum in parallel with 0.1µF or 10µF ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground for Internal Logic. Tie to AGND. D5 to D0 (Pins 15 to 20): Three-State Data Outputs. SHDN (Pin 21): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by CS. CS = 0 for nap mode and CS = 1 for sleep mode. RD (Pin 22): Read Input. This enables the output drivers when CS is low. 14-BIT CAPACITIVE DAC COMP REF AMP 2.5V REF 2k REFCOMP (4.06V) CSAMPLE CSAMPLE • • • D13 D0 BUSY CONTROL LOGIC CS CONVST RD SHDN INTERNAL CLOCK ZEROING SWITCHES DVDD VSS AVDD +AIN –AIN VREF AGND DGND 14 1419 BD + – SUCCESSIVE APPROXIMATION REGISTER OUTPUT LATCHES FU CTIO AL BLOCK DIAGRA |
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