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LTC3901 Datasheet(PDF) 8 Page - Linear Technology |
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LTC3901 Datasheet(HTML) 8 Page - Linear Technology |
8 / 16 page LTC3901 8 3901f polarity. In some situations, for example during power-up or power-down, the SYNC pulse magnitude may be low (slightly higher or lower than the threshold of the compara- tors). This can cause only one of the SYNC comparators to trip. This also appears as a double pulse to the sequential logic and both drivers will be shut off. Current Sense The differential input current sense comparators, ISE and ISF (Figure 6), are used for sensing the voltage across the drain-to-source terminal of the MOSFET through the CSX+ and CSX– pins. There are two sets of comparator inputs, one for each MOSFET (ME and MF). If the inductor current reverses into the MOSFET causing CSX+ to rise above CSX– by more than 10.5mV, the LTC3901 turns off the respective MOSFET. This comparator is used to prevent inductor reverse current buildup during power-down or Burst Mode operation, which may cause damage to the MOSFETs. The 10.5mV input threshold has a positive temperature coefficient, which closely matches the TC of the external MOSFET RDS(ON). The current sense com- parator is only active 250ns after the respective driver APPLICATIO S I FOR ATIO The timeout period is determined predominantly by the external RTMR and CTMR values and is independent of the VCC voltage. This independence is achieved by making the timeout threshold a ratio of VCC. The ratio is 0.2x, set internally by R1 and R2 (see Figure 3). The Timeout period should be programmed to around 1 period of the primary switching frequency using the following formula: TIMEOUT = 0.2 • RTMR • CTMR + 0.27E-06 To reduce error in the timeout setting due to the discharge time, select CTMR between 100pF and 1000pF. Start with a CTMR around 470pF and then calculate the required RTMR. CTMR should be placed as close as possible to the LTC3901 with minimum PCB trace between CTMR, the TIMER pin and GND. This is to reduce any ringing caused by the PCB trace inductance when CTMR discharges. This ringing may introduce error to the timeout setting. The timer input also includes a current sinking clamp circuit (ZTMR in Figure 3) that clamps this pin to about 0.5 • VCC if there is missing SYNC/timer reset pulse. This clamp circuit prevents the timer capacitor from getting fully charged up to the rail, which would result in a longer discharge time. The current sinking capability of the circuit is around 1mA. The timeout function can be disabled by connecting the timer pin to GND. Synchronization Sequence A typical push-pull converter cycle always turns off ME and MF alternately. The SYNC input should alternate between a positive and negative pulse. The LTC3901 includes a sequential logic to monitor the SYNC input pulses. If after one positive pulse the SYNC comparator receives another positive pulse, the LTC3901 sequential logic shuts off both drivers until a negative pulse appears. The same applies to double negative pulses; the driver will turn on only after receiving a positive pulse. This is to protect the external components in situations where only one polarity of the SYNC pulse is present and the corre- sponding driver remains on. Figure 5 shows the SYNC double pulse operation. The LTC3901 has two separate SYNC comparators (S+ and S– in the Block Diagram) to detect the positive and nega- tive pulses. The threshold voltages of both comparators are designed to be of the same magnitude but opposite in SYNC ME MF 3901 F05 0V EXPECTED POSITIVE SYNC PULSE, MF PULLS HIGH SECOND NEGATIVE SYNC PULSE, BOTH ME AND MF PULL LOW Figure 5. SYNC Double Pulse Operation + – 6 5 RCSE1 T1 RCSE2 CSE+ ISE ISF CSE– ZCSE 11V 10.5mV LTC3901 ME RCSE3 11 12 RCSF1 RCSF2 CSF+ CSF– MF 3901 F06 RCSF3 + – ZCSF 11V 10.5mV Figure 6. Current Sense Circuit |
Similar Part No. - LTC3901_15 |
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Similar Description - LTC3901_15 |
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