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LTC1287CIN Datasheet(PDF) 10 Page - Linear Technology |
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LTC1287CIN Datasheet(HTML) 10 Page - Linear Technology |
10 / 16 page 10 LTC1287 DOUT CLK B11 HI-Z B9 B10 LTC1287 F8a CS 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME tSUCS tWHCS tSMPL (+) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT DOUT CLK B11 HI-Z B9 B10 LTC1287 F8b CS 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME tWHCS tSMPL (+) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT “+” Input Settling The input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figures 8a, 8b and 8c). The sample period can be as short as tWHCS + 0.5 CLK cycle or as long as tWHCS + 1.5 CLK cycles before a conversion starts. This variability depends on where CS falls relative to CLK. The voltage on the “+” input must settle completely within the sample period. Minimizing RSOURCE+ and C1 will improve the settling time. If large “+” input source S APPLICATI I FOR ATIO resistance must be used, the sample time can be increased by using a slower CLK frequency. With the minimum possible sample time of 6.0 µs, RSOURCE+ < 4.0k and C1 < 20pF will provide adequate settle time. “–” Input Settling At the end of the sample phase the input capacitor switches to the “–” input and the conversion starts (see Figures 8a, 8b and 8c). During the conversion, the “+” input voltage is “+” and “–” Input Settling Windows Figure 8b. Setup Time (tSUCS) is Met Figure 8a. Setup Time (tSUCS) is Met |
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