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LTC1278-4CN Datasheet(PDF) 8 Page - Linear Technology |
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LTC1278-4CN Datasheet(HTML) 8 Page - Linear Technology |
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8 / 16 page  8 LTC1278 CONVERSION DETAILS The LTC1278 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microproces- sors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of conversion the successive approxi- mation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor during the acquire phase, and the comparator TEST CIRCUITS Load Circuits for Output Float Delay Load Circuits for Access Timing 3k CL DBN DGND A) HIGH-Z TO VOH (t8) AND VOL TO VOH (t6) CL DBN 3k 5V B) HIGH-Z TO VOL (t8) AND VOH TO VOL (t6) DGND LTC1278 TA08 3k 10pF DBN DGND A) VOH TO HIGH-Z 10pF DBN 3k 5V B) VOL TO HIGH-Z DGND 1278 • TA08 SHDN to CONVST Wake-Up Timing t3 SHDN CONVST LTC1278 • TC03 APPLICATIONS INFORMATION offset is nulled by the feedback switch. In this acquire phase, a minimum delay of 200ns will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the comparator feedback switch opens, putting the comparator into the VDAC LTC1278 F1 + – CDAC DAC SAMPLE HOLD CSAMPLE S A R 12-BIT LATCH COMPARATOR SAMPLE SI AIN Figure 1. AIN Input CS to RD Setup Timing t1 CS RD LTC1278 • TC01 CS to CONVST Setup Timing t2 CS CONVST LTC1278 • TC02 TI I G DIAGRA S |
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