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LTC1267CG Datasheet(PDF) 10 Page - Linear Technology |
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LTC1267CG Datasheet(HTML) 10 Page - Linear Technology |
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10 / 16 page  10 LTC1267 LTC1267-ADJ/LTC1267-ADJ5 APPLICATIO S I FOR ATIO Where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses, while the P-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The N-channel MOSFET losses are the greatest at high input voltage or during a short circuit when the N-channel duty cycle is nearly 100%. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.007/ °C can be used as an approximation for low voltage MOSFETs. CRSS isusuallyspecifiedinthe MOSFET electrical characteristics. The constant k = 5 can be used for the LTC1267 to estimate the relative contributions of the two terms in the P-channel dissipation equation. The Schottky diodes D3 and D5 shown in Figure 1 only conduct during the dead-time between the conduction of the respective power MOSFETs. The sole purpose of D3 and D5 is to prevent the body diode of the N-channel MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency (although there are no other harmful effects if D3 and D5 are omitted). Therefore, D3 and D5 should be selected for a forward voltage of less than 0.6V when conducting IMAX. CIN and COUT Selection In continuous mode, the source current of the P-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capaci- tor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ IMAX [VOUT(VIN – VOUT)]1/2 VIN This formula has a maximum at VIN = 2VOUT where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. An additional 0.1 µF ceramic capacitor is also required on VIN for high frequency decoupling. The selection of COUT is driven by the required Effective Series Resistance (ESR). The ESR of COUT must be less than twice the value of RSENSE for proper operation of the LTC1267: COUT Required ESR < 2RSENSE Optimum efficiency is obtained by making the ESR equal to RSENSE. As the ESR is increased up to 2RSENSE, the efficiency degrades by less than 1%. If the ESR is greater than 2RSENSE, the voltage ripple on the output capacitor will prematurely trigger Burst Modeoperation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. Manufacturers such as Nichicon, United Chemicon, and Sprague should be considered for high performance ca- pacitors. In surface mount applications multiple capaci- tors may have to be paralleled to meet the capacitance, ESR, or RMS current handling requirements of the appli- cation. For additional information regarding capacitor selection, please refer to the LTC1159 data sheet. At low supply voltages, a minimum capacitance at COUT is needed to prevent an abnormal low frequency operating mode (see Figure 4). When COUT is made too small, the output ripple at low frequencies will be large enough to trip Figure 4. Minimum Suggested COUT (VIN – VOUT) VOLTAGE (V) 0 1000 800 600 400 200 0 4 LTC1267 • F04 1 2 3 5 L = 50 µH RSENSE = 0.02Ω L = 25 µH RSENSE = 0.02Ω L = 50 µH RSENSE = 0.05Ω |
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