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LTC1164-7M Datasheet(PDF) 9 Page - Linear Technology |
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LTC1164-7M Datasheet(HTML) 9 Page - Linear Technology |
9 / 12 page 9 LTC1164-7 and 5 should be biased at 1/2 supply and should be bypassed to the analog ground plane with at least a 1 µF capacitor (Figure 3). For single 5V operation at the highest fCLK of 2MHz, pins 3 and 5 should be biased at 2V. This minimizes passband gain and phase variations. Ratio Input Pin (10) The DC level at this pin determines the ratio of the clock frequency to the cutoff frequency of the filter. Pin 10 at V + gives a 50:1 ratio and pin 10 at V – gives a 100:1 ratio. For single supply operation the ratio is 50:1 when pin 10 is at V + and 100:1 when pin 10 is at ground. When pin 10 is not tied to ground, it should be bypassed to analog ground with a 0.1 µF capacitor. If the DC level at pin 10 is switched mechanically or electrically at slew rates greater than 1V/ µs while the device is operating, a 10k resistor should be connected between pin 10 and the DC source. Filter Input Pin (2) The input pin is connected internally through a 50k resis- tor tied to the inverting input of an op amp. Filter Output Pins (9, 6) Pin 9 is the specified output of the filter; it can typically source/sink 1mA. Driving coaxial cables or resistive loads less than 20k will degrade the total harmonic distortion of the filter. When evaluating the device’s distortion an output buffer is required. A noninverting buffer, Figure 4, can be used provided that its input common-mode range is well within the filter’s output swing. Pin 6 is an interme- diate filter output providing an unspecified 6th order lowpass filter. Pin 6 should not be loaded. PI FU CTIO S Table 7. Clock Source High and Low Threshold Levels POWER SUPPLY HIGH LEVEL LOW LEVEL Dual Supply = ±7.5V ≥ 2.18V ≤ 0.5V Dual Supply = ±5V ≥ 1.45V ≤ 0.5V Dual Supply = ±2.5V ≥ 0.73V ≤ – 2.0V Single Supply = 12V ≥ 7.80V ≤ 6.5V Single Supply = 5V ≥ 1.45V ≤ 0.5V Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 50:1 Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 50:1 Analog Ground Pins (3, 5) The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the pack- age is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation, pins 3 and 5 should be connected to the analog ground plane. For single supply operation, pins 3 Figure 4. Buffer for Filter Output 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VIN V+ 1k VOUT DIGITAL SUPPLY + GND CLOCK SOURCE 1164-7 F03 + LTC1164-7 0.1 µF 1 µF 10k 10k V+ 1k 1164-7 F04 LT1056 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VIN V+ 1k V– VOUT LTC1164-7 DIGITAL SUPPLY + GND CLOCK SOURCE 1164-7 F02 0.1 µF 0.1 µF V+ |
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Similar Description - LTC1164-7M |
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